| Message ID | 20250214165724.184599-1-18255117159@163.com (mailing list archive) |
|---|---|
| State | New |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | [v4] PCI: cadence-ep: Fix the driver to send MSG TLP for INTx without data payload | expand |
On Sat, Feb 15, 2025 at 12:57:24AM +0800, Hans Zhang wrote: > Cadence reference manual cdn_pcie_gen4_hpa_axi_ips_ug_v1.04.pdf, section > 9.1.7.1 'AXI Subordinate to PCIe Address Translation' mentions that > axi_s_awaddr bits 16 when set, corresponds to MSG with data and when not > set, MSG without data. > > But the driver is doing the opposite and due to this, INTx is never > received on the host. So fix the driver to reflect the documentation and > also make INTx work. > > Fixes: 37dddf14f1ae ("PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller") > Signed-off-by: Hans Zhang <18255117159@163.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> - Mani > --- > Changes since v3: > https://lore.kernel.org/linux-pci/20250207103923.32190-1-18255117159@163.com/ > > - Add Fixes: tag. > - The patch subject and commit message were modified. > > Changes since v1-v2: > - Change email number and Signed-off-by > --- > drivers/pci/controller/cadence/pcie-cadence-ep.c | 3 +-- > drivers/pci/controller/cadence/pcie-cadence.h | 2 +- > 2 files changed, 2 insertions(+), 3 deletions(-) > > diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c > index e0cc4560dfde..0bf4cde34f51 100644 > --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c > +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c > @@ -352,8 +352,7 @@ static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 intx, > spin_unlock_irqrestore(&ep->lock, flags); > > offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) | > - CDNS_PCIE_NORMAL_MSG_CODE(msg_code) | > - CDNS_PCIE_MSG_NO_DATA; > + CDNS_PCIE_NORMAL_MSG_CODE(msg_code); > writel(0, ep->irq_cpu_addr + offset); > } > > diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h > index f5eeff834ec1..39ee9945c903 100644 > --- a/drivers/pci/controller/cadence/pcie-cadence.h > +++ b/drivers/pci/controller/cadence/pcie-cadence.h > @@ -246,7 +246,7 @@ struct cdns_pcie_rp_ib_bar { > #define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) > #define CDNS_PCIE_NORMAL_MSG_CODE(code) \ > (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) > -#define CDNS_PCIE_MSG_NO_DATA BIT(16) > +#define CDNS_PCIE_MSG_DATA BIT(16) > > struct cdns_pcie; > > > -- > 2.25.1 >
diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci/controller/cadence/pcie-cadence-ep.c index e0cc4560dfde..0bf4cde34f51 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -352,8 +352,7 @@ static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 intx, spin_unlock_irqrestore(&ep->lock, flags); offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) | - CDNS_PCIE_NORMAL_MSG_CODE(msg_code) | - CDNS_PCIE_MSG_NO_DATA; + CDNS_PCIE_NORMAL_MSG_CODE(msg_code); writel(0, ep->irq_cpu_addr + offset); } diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h index f5eeff834ec1..39ee9945c903 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -246,7 +246,7 @@ struct cdns_pcie_rp_ib_bar { #define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) #define CDNS_PCIE_NORMAL_MSG_CODE(code) \ (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) -#define CDNS_PCIE_MSG_NO_DATA BIT(16) +#define CDNS_PCIE_MSG_DATA BIT(16) struct cdns_pcie;
Cadence reference manual cdn_pcie_gen4_hpa_axi_ips_ug_v1.04.pdf, section 9.1.7.1 'AXI Subordinate to PCIe Address Translation' mentions that axi_s_awaddr bits 16 when set, corresponds to MSG with data and when not set, MSG without data. But the driver is doing the opposite and due to this, INTx is never received on the host. So fix the driver to reflect the documentation and also make INTx work. Fixes: 37dddf14f1ae ("PCI: cadence: Add EndPoint Controller driver for Cadence PCIe controller") Signed-off-by: Hans Zhang <18255117159@163.com> --- Changes since v3: https://lore.kernel.org/linux-pci/20250207103923.32190-1-18255117159@163.com/ - Add Fixes: tag. - The patch subject and commit message were modified. Changes since v1-v2: - Change email number and Signed-off-by --- drivers/pci/controller/cadence/pcie-cadence-ep.c | 3 +-- drivers/pci/controller/cadence/pcie-cadence.h | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-)