diff mbox series

[v7,4/7] arm64: dts: agilex: move bus@80000000 to socfpga_agilex.dtsi

Message ID 20250215155359.321513-5-matthew.gerlach@linux.intel.com (mailing list archive)
State New
Delegated to: Krzysztof Wilczyński
Headers show
Series Add PCIe Root Port support for Agilex family of chips | expand

Commit Message

Matthew Gerlach Feb. 15, 2025, 3:53 p.m. UTC 
The bus from HPS to the FPGA is part of the SoC. Move its
device tree node to socfpga_agilex.dtsi to allow it to be
referenced by any board.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
v7:
 - Fix sorting of nodes.

v6:
 - New patch to series.
---
 arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 10 +++++++
 .../boot/dts/intel/socfpga_agilex_n6000.dts   | 30 +++++++------------
 2 files changed, 21 insertions(+), 19 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index 202b4404577e..3f4fb9cb312f 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -678,5 +678,15 @@  qspi: spi@ff8d2000 {
 
 			status = "disabled";
 		};
+
+		bus80000000: bus@80000000 {
+			compatible = "simple-bus";
+			reg = <0x80000000 0x60000000>,
+			      <0xf9000000 0x00100000>;
+			reg-names = "axi_h2f", "axi_h2f_lw";
+			#address-cells = <2>;
+			#size-cells = <1>;
+			ranges = <0x00000000 0x00000000 0x00000000 0x00000000>;
+		};
 	};
 };
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
index 55f825c5245f..62d2b3febbdd 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
@@ -25,26 +25,22 @@  memory@80000000 {
 		/* We expect the bootloader to fill in the reg */
 		reg = <0 0x80000000 0 0>;
 	};
+};
 
-	soc@0 {
-		bus@80000000 {
-			compatible = "simple-bus";
-			reg = <0x80000000 0x60000000>,
-				<0xf9000000 0x00100000>;
-			reg-names = "axi_h2f", "axi_h2f_lw";
-			#address-cells = <2>;
-			#size-cells = <1>;
-			ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
+&bus80000000 {
+	ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>;
 
-			dma-controller@0 {
-				compatible = "intel,hps-copy-engine";
-				reg = <0x00000000 0x00000000 0x00001000>;
-				#dma-cells = <1>;
-			};
-		};
+	dma-controller@0 {
+		compatible = "intel,hps-copy-engine";
+		reg = <0x00000000 0x00000000 0x00001000>;
+		#dma-cells = <1>;
 	};
 };
 
+&fpga_mgr {
+	status = "disabled";
+};
+
 &osc1 {
 	clock-frequency = <25000000>;
 	status = "okay";
@@ -61,7 +57,3 @@  &uart1 {
 &watchdog0 {
 	status = "okay";
 };
-
-&fpga_mgr {
-	status = "disabled";
-};