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[v7,5/7] arm64: dts: agilex: add dtsi for PCIe Root Port

Message ID 20250215155359.321513-6-matthew.gerlach@linux.intel.com (mailing list archive)
State New
Delegated to: Krzysztof Wilczyński
Headers show
Series Add PCIe Root Port support for Agilex family of chips | expand

Commit Message

Matthew Gerlach Feb. 15, 2025, 3:53 p.m. UTC 
Add the base device tree for support of the PCIe Root Port
for the Agilex family of chips.

Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
---
v7:
 - Change value of #interrupt-cells to decimal.

v6:
 - Reference bus80000000 in socfpga_agilex.dtsi
 - Change values of #address-cells, #size-cell, and num-vectors to decimal
 - Fix SPDX header.
 - Fix checkpatch.pl line length warning.
 - Fix "address format error" from dtschema check.

v3:
 - Remove accepted patches from patch set.

v2:
 - Rename node to fix schema check error.
---
 .../intel/socfpga_agilex_pcie_root_port.dtsi  | 48 +++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
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Patch

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
new file mode 100644
index 000000000000..5333bd3fe535
--- /dev/null
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
@@ -0,0 +1,48 @@ 
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024, Intel Corporation
+ */
+&bus80000000 {
+	ranges = <0x00000000 0x00000000 0x80000000 0x00040000>,
+		 <0x00000000 0x10000000 0x90100000 0x0ff00000>,
+		 <0x00000000 0x20000000 0xa0000000 0x00200000>,
+		 <0x00000001 0x00010000 0xf9010000 0x00008000>,
+		 <0x00000001 0x00018000 0xf9018000 0x00000080>,
+		 <0x00000001 0x00018080 0xf9018080 0x00000010>;
+
+	pcie_0_pcie_aglx: pcie@10000000 {
+		reg = <0x00000000 0x10000000 0x10000000>,
+		      <0x00000001 0x00010000 0x00008000>,
+		      <0x00000000 0x20000000 0x00200000>;
+		reg-names = "Txs", "Cra", "Hip";
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 0x14 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		device_type = "pci";
+		bus-range = <0x0000000 0x000000ff>;
+		ranges = <0x82000000 0x00000000 0x00100000 0x00000000
+			  0x10000000 0x00000000 0x0ff00000>;
+		msi-parent = <&pcie_0_msi_irq>;
+		#address-cells = <3>;
+		#size-cells = <2>;
+		interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+		interrupt-map = <0x0 0x0 0x0 0x1 &pcie_0_pcie_aglx 0 0 0 0x1>,
+				<0x0 0x0 0x0 0x2 &pcie_0_pcie_aglx 0 0 0 0x2>,
+				<0x0 0x0 0x0 0x3 &pcie_0_pcie_aglx 0 0 0 0x3>,
+				<0x0 0x0 0x0 0x4 &pcie_0_pcie_aglx 0 0 0 0x4>;
+		status = "disabled";
+	};
+
+	pcie_0_msi_irq: msi@100018080 {
+		compatible = "altr,msi-1.0";
+		reg = <0x00000001 0x00018080 0x00000010>,
+		      <0x00000001 0x00018000 0x00000080>;
+		reg-names = "csr", "vector_slave";
+		interrupt-parent = <&intc>;
+		interrupts = <GIC_SPI 0x13 IRQ_TYPE_LEVEL_HIGH>;
+		msi-controller;
+		num-vectors = <32>;
+		status = "disabled";
+	};
+};