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[V3,1/2] schemas: pci: bridge: Document PCI L0s & L1 entry delay

Message ID 20250216014510.3990613-2-krishna.chundru@oss.qualcomm.com (mailing list archive)
State New
Delegated to: Krzysztof Wilczyński
Headers show
Series schemas: pci: bridge: Document PCI L0s & L1 entry delay and N_FTS | expand

Commit Message

Krishna Chaitanya Chundru Feb. 16, 2025, 1:45 a.m. UTC 
Some controllers and endpoints provide provision to program the entry
delays of L0s & L1 which will allow the link to enter L0s & L1 more
aggressively to save power.

These values needs to be programmed before link training.

Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
---
 dtschema/schemas/pci/pci-bus-common.yaml | 6 ++++++
 1 file changed, 6 insertions(+)
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Patch

diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pci/pci-bus-common.yaml
index 94b648f..a9309af 100644
--- a/dtschema/schemas/pci/pci-bus-common.yaml
+++ b/dtschema/schemas/pci/pci-bus-common.yaml
@@ -150,6 +150,12 @@  properties:
     description: Disables ASPM L0s capability
     type: boolean
 
+  aspm-l0s-entry-delay-ns:
+    description: ASPM L0s entry delay
+
+  aspm-l1-entry-delay-ns:
+    description: ASPM L1 entry delay
+
   vpcie12v-supply:
     description: 12v regulator phandle for the slot