diff mbox series

[v5,3/3] PCI: xilinx-cpm: Add support for Versal Net CPM5NC Root Port controller

Message ID 20250224155025.782179-4-thippeswamy.havalige@amd.com (mailing list archive)
State Accepted
Delegated to: Krzysztof Wilczyński
Headers show
Series Add support for Versal Net CPM5N Root Port controller | expand

Commit Message

Havalige, Thippeswamy Feb. 24, 2025, 3:50 p.m. UTC 
The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices
incorporate the Coherency and PCIe Gen5 Module, specifically the
Next-Generation Compact Module (CPM5NC).

The integrated CPM5NC block, along with the built-in bridge, can function
as a PCIe Root Port & supports the PCIe Gen5 protocol with data transfer
rates of up to 32 GT/s, capable of supporting up to a x16 lane-width
configuration.

Bridge errors are managed using a specific interrupt line designed for
CPM5N. INTx interrupt support is not available.

Currently in this commit platform specific Bridge errors support is not
added.

Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
Changes in v2:
- Update commit message.
Changes in v3:
- Address review comments.
Changes in v4:
- Add reviewed by.
---
 drivers/pci/controller/pcie-xilinx-cpm.c | 40 +++++++++++++++++-------
 1 file changed, 29 insertions(+), 11 deletions(-)

Comments

Bjorn Helgaas March 10, 2025, 5:07 p.m. UTC | #1 
On Mon, Feb 24, 2025 at 09:20:24PM +0530, Thippeswamy Havalige wrote:
> The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices
> incorporate the Coherency and PCIe Gen5 Module, specifically the
> Next-Generation Compact Module (CPM5NC).
> 
> The integrated CPM5NC block, along with the built-in bridge, can function
> as a PCIe Root Port & supports the PCIe Gen5 protocol with data transfer
> rates of up to 32 GT/s, capable of supporting up to a x16 lane-width
> configuration.
> 
> Bridge errors are managed using a specific interrupt line designed for
> CPM5N. INTx interrupt support is not available.
> 
> Currently in this commit platform specific Bridge errors support is not
> added.

> @@ -478,6 +479,9 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
>  {
>  	const struct xilinx_cpm_variant *variant = port->variant;
>  
> +	if (variant->version != CPM5NC_HOST)
> +		return;

You're adding support for CPM5NC_HOST, but this changes the behavior
for all the NON-CPM5NC_HOST devices, which looks like a typo.

Should it be "variant->version == CPM5NC_HOST" instead?

>  	if (cpm_pcie_link_up(port))
>  		dev_info(port->dev, "PCIe Link is UP\n");
>  	else
> @@ -578,9 +582,13 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
>  
>  	port->dev = dev;
>  
> -	err = xilinx_cpm_pcie_init_irq_domain(port);
> -	if (err)
> -		return err;
> +	port->variant = of_device_get_match_data(dev);
> +
> +	if (port->variant->version != CPM5NC_HOST) {
> +		err = xilinx_cpm_pcie_init_irq_domain(port);

  xilinx_cpm_pcie_init_port()
  {
    if (variant->version != CPM5NC_HOST)
      return;
    ...

  xilinx_cpm_pcie_probe()
  {
    ...
    if (port->variant->version != CPM5NC_HOST) {
      err = xilinx_cpm_pcie_init_irq_domain(port);
    ...
    xilinx_cpm_pcie_init_port();
    ...
    if (port->variant->version != CPM5NC_HOST) {
      err = xilinx_cpm_setup_irq(port);
    ...
  err_host_bridge:
    if (port->variant->version != CPM5NC_HOST)
      xilinx_cpm_free_interrupts(port);
    ...
  err_free_irq_domains:
    if (port->variant->version != CPM5NC_HOST)
      xilinx_cpm_free_irq_domains(port);

Right now one CPM5NC_HOST test is inside xilinx_cpm_pcie_init_port()
all the others are in xilinx_cpm_pcie_probe().

I think it would be nicer if the tests were inside
xilinx_cpm_pcie_init_irq_domain(), xilinx_cpm_setup_irq(),
xilinx_cpm_free_interrupts(), and xilinx_cpm_free_irq_domains() so
they're all done the same way and they're closer to the actual
differences instead of cluttering xilinx_cpm_pcie_probe().

Also, this makes it look like CPM5NC_HOST doesn't support any
interrupts at all.  No INTx, no MSI, no MSI-X.  Is that true?  If so,
what good is a host controller where interrupts don't work?

Bjorn
Bjorn Helgaas March 11, 2025, 3:59 p.m. UTC | #2 
On Mon, Mar 10, 2025 at 12:07:17PM -0500, Bjorn Helgaas wrote:
> On Mon, Feb 24, 2025 at 09:20:24PM +0530, Thippeswamy Havalige wrote:
> > The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices
> > incorporate the Coherency and PCIe Gen5 Module, specifically the
> > Next-Generation Compact Module (CPM5NC).
> > 
> > The integrated CPM5NC block, along with the built-in bridge, can function
> > as a PCIe Root Port & supports the PCIe Gen5 protocol with data transfer
> > rates of up to 32 GT/s, capable of supporting up to a x16 lane-width
> > configuration.
> > 
> > Bridge errors are managed using a specific interrupt line designed for
> > CPM5N. INTx interrupt support is not available.
> > 
> > Currently in this commit platform specific Bridge errors support is not
> > added.
> 
> > @@ -478,6 +479,9 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
> >  {
> >  	const struct xilinx_cpm_variant *variant = port->variant;
> >  
> > +	if (variant->version != CPM5NC_HOST)
> > +		return;
> 
> You're adding support for CPM5NC_HOST, but this changes the behavior
> for all the NON-CPM5NC_HOST devices, which looks like a typo.
> 
> Should it be "variant->version == CPM5NC_HOST" instead?

Thanks for your patch that fixes this part.

> Also, this makes it look like CPM5NC_HOST doesn't support any
> interrupts at all.  No INTx, no MSI, no MSI-X.  Is that true?  If so,
> what good is a host controller where interrupts don't work?

Does this controller support interrupts?
Havalige, Thippeswamy March 11, 2025, 4:21 p.m. UTC | #3 
[AMD Official Use Only - AMD Internal Distribution Only]

Hi Bjorn,

> -----Original Message-----
> From: Bjorn Helgaas <helgaas@kernel.org>
> Sent: Tuesday, March 11, 2025 9:30 PM
> To: Havalige, Thippeswamy <thippeswamy.havalige@amd.com>
> Cc: bhelgaas@google.com; lpieralisi@kernel.org; kw@linux.com;
> manivannan.sadhasivam@linaro.org; robh@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org; linux-pci@vger.kernel.org; devicetree@vger.kernel.org;
> linux-kernel@vger.kernel.org; Simek, Michal <michal.simek@amd.com>;
> Gogada, Bharat Kumar <bharat.kumar.gogada@amd.com>
> Subject: Re: [PATCH v5 3/3] PCI: xilinx-cpm: Add support for Versal Net CPM5NC
> Root Port controller
>
> On Mon, Mar 10, 2025 at 12:07:17PM -0500, Bjorn Helgaas wrote:
> > On Mon, Feb 24, 2025 at 09:20:24PM +0530, Thippeswamy Havalige wrote:
> > > The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices
> > > incorporate the Coherency and PCIe Gen5 Module, specifically the
> > > Next-Generation Compact Module (CPM5NC).
> > >
> > > The integrated CPM5NC block, along with the built-in bridge, can function
> > > as a PCIe Root Port & supports the PCIe Gen5 protocol with data transfer
> > > rates of up to 32 GT/s, capable of supporting up to a x16 lane-width
> > > configuration.
> > >
> > > Bridge errors are managed using a specific interrupt line designed for
> > > CPM5N. INTx interrupt support is not available.
> > >
> > > Currently in this commit platform specific Bridge errors support is not
> > > added.
> >
> > > @@ -478,6 +479,9 @@ static void xilinx_cpm_pcie_init_port(struct
> xilinx_cpm_pcie *port)
> > >  {
> > >   const struct xilinx_cpm_variant *variant = port->variant;
> > >
> > > + if (variant->version != CPM5NC_HOST)
> > > +         return;
> >
> > You're adding support for CPM5NC_HOST, but this changes the behavior
> > for all the NON-CPM5NC_HOST devices, which looks like a typo.
> >
> > Should it be "variant->version == CPM5NC_HOST" instead?
>
> Thanks for your patch that fixes this part.
>
> > Also, this makes it look like CPM5NC_HOST doesn't support any
> > interrupts at all.  No INTx, no MSI, no MSI-X.  Is that true?  If so,
> > what good is a host controller where interrupts don't work?
>
> Does this controller support interrupts?

Yes, CPM5NC controller supports MSI & MSI-X via gic-its.

Regards,
Thippeswamy H
diff mbox series

Patch

diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c
index 660b12fc4631..55a8b14473be 100644
--- a/drivers/pci/controller/pcie-xilinx-cpm.c
+++ b/drivers/pci/controller/pcie-xilinx-cpm.c
@@ -84,6 +84,7 @@  enum xilinx_cpm_version {
 	CPM,
 	CPM5,
 	CPM5_HOST1,
+	CPM5NC_HOST,
 };
 
 /**
@@ -478,6 +479,9 @@  static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
 {
 	const struct xilinx_cpm_variant *variant = port->variant;
 
+	if (variant->version != CPM5NC_HOST)
+		return;
+
 	if (cpm_pcie_link_up(port))
 		dev_info(port->dev, "PCIe Link is UP\n");
 	else
@@ -578,9 +582,13 @@  static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
 
 	port->dev = dev;
 
-	err = xilinx_cpm_pcie_init_irq_domain(port);
-	if (err)
-		return err;
+	port->variant = of_device_get_match_data(dev);
+
+	if (port->variant->version != CPM5NC_HOST) {
+		err = xilinx_cpm_pcie_init_irq_domain(port);
+		if (err)
+			return err;
+	}
 
 	bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
 	if (!bus) {
@@ -588,8 +596,6 @@  static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	port->variant = of_device_get_match_data(dev);
-
 	err = xilinx_cpm_pcie_parse_dt(port, bus->res);
 	if (err) {
 		dev_err(dev, "Parsing DT failed\n");
@@ -598,10 +604,12 @@  static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
 
 	xilinx_cpm_pcie_init_port(port);
 
-	err = xilinx_cpm_setup_irq(port);
-	if (err) {
-		dev_err(dev, "Failed to set up interrupts\n");
-		goto err_setup_irq;
+	if (port->variant->version != CPM5NC_HOST) {
+		err = xilinx_cpm_setup_irq(port);
+		if (err) {
+			dev_err(dev, "Failed to set up interrupts\n");
+			goto err_setup_irq;
+		}
 	}
 
 	bridge->sysdata = port->cfg;
@@ -614,11 +622,13 @@  static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
 	return 0;
 
 err_host_bridge:
-	xilinx_cpm_free_interrupts(port);
+	if (port->variant->version != CPM5NC_HOST)
+		xilinx_cpm_free_interrupts(port);
 err_setup_irq:
 	pci_ecam_free(port->cfg);
 err_parse_dt:
-	xilinx_cpm_free_irq_domains(port);
+	if (port->variant->version != CPM5NC_HOST)
+		xilinx_cpm_free_irq_domains(port);
 	return err;
 }
 
@@ -641,6 +651,10 @@  static const struct xilinx_cpm_variant cpm5_host1 = {
 	.ir_enable = XILINX_CPM_PCIE1_IR_ENABLE,
 };
 
+static const struct xilinx_cpm_variant cpm5n_host = {
+	.version = CPM5NC_HOST,
+};
+
 static const struct of_device_id xilinx_cpm_pcie_of_match[] = {
 	{
 		.compatible = "xlnx,versal-cpm-host-1.00",
@@ -654,6 +668,10 @@  static const struct of_device_id xilinx_cpm_pcie_of_match[] = {
 		.compatible = "xlnx,versal-cpm5-host1",
 		.data = &cpm5_host1,
 	},
+	{
+		.compatible = "xlnx,versal-cpm5nc-host",
+		.data = &cpm5n_host,
+	},
 	{}
 };