Message ID | 20250320110854.3866284-2-michal.winiarski@intel.com (mailing list archive) |
---|---|
State | New |
Delegated to: | Bjorn Helgaas |
Headers | show |
Series | PCI: VF resizable BAR | expand |
On Thu, 20 Mar 2025, Michał Winiarski wrote: > Similar to regular resizable BAR, VF BAR can also be resized, e.g. by > the system firmware or the PCI subsystem itself. > > Add the capability ID and restore it as a part of IOV state. > > See PCIe r4.0, sec 9.3.7.4. Usually it's best o refer to latest gen doc, the section number seems to be the same also in r6.2. This didn't refer to spec section that specified VF Rebar ext capability (7.8.7) though. I think it should and it would also be good to mention the capability layout is the same as with the rebar cap. > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> > Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> > Reviewed-by: Christian König <christian.koenig@amd.com> > --- > drivers/pci/iov.c | 30 +++++++++++++++++++++++++++++- > drivers/pci/pci.h | 1 + > include/uapi/linux/pci_regs.h | 1 + > 3 files changed, 31 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c > index 121540f57d4bf..bf95387993cd5 100644 > --- a/drivers/pci/iov.c > +++ b/drivers/pci/iov.c > @@ -7,6 +7,7 @@ > * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com> > */ > > +#include <linux/bitfield.h> > #include <linux/pci.h> > #include <linux/slab.h> > #include <linux/export.h> > @@ -830,6 +831,7 @@ static int sriov_init(struct pci_dev *dev, int pos) > pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link); > if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) > iov->link = PCI_DEVFN(PCI_SLOT(dev->devfn), iov->link); > + iov->vf_rebar_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_VF_REBAR); > > if (pdev) > iov->dev = pci_dev_get(pdev); > @@ -868,6 +870,30 @@ static void sriov_release(struct pci_dev *dev) > dev->sriov = NULL; > } > > +static void sriov_restore_vf_rebar_state(struct pci_dev *dev) > +{ > + unsigned int pos, nbars, i; > + u32 ctrl; > + > + pos = dev->sriov->vf_rebar_cap; > + if (!pos) > + return; > + > + pci_read_config_dword(dev, pos + PCI_REBAR_CTRL, &ctrl); > + nbars = FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); > + > + for (i = 0; i < nbars; i++, pos += 8) { > + int bar_idx, size; > + > + pci_read_config_dword(dev, pos + PCI_REBAR_CTRL, &ctrl); > + bar_idx = FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl); > + size = pci_rebar_bytes_to_size(dev->sriov->barsz[bar_idx]); > + ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; > + ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); > + pci_write_config_dword(dev, pos + PCI_REBAR_CTRL, ctrl); I started to wonder if we'd still want to have the VF Rebar ones in uapi/linux/pci_regs.h (despite the same capability layout): /* * PCI Resizable BAR and PCI VF Resizable BAR extended capabilities have * the same layout of fields. */ #define PCI_VF_REBAR_CTRL PCI_REBAR_CTRL #define PCI_VF_REBAR_CTRL_BAR_IDX PCI_REBAR_CTRL_BAR_IDX etc. as then it would be possible grep to pick up only the relevant lines. I'd not duplicate _SHIFT defines though. FIELD_PREP/GET() in general does not need _SHIFT defines at all and they are just duplicated information. > + } > +} > + > static void sriov_restore_state(struct pci_dev *dev) > { > int i; > @@ -1027,8 +1053,10 @@ resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno) > */ > void pci_restore_iov_state(struct pci_dev *dev) > { > - if (dev->is_physfn) > + if (dev->is_physfn) { > + sriov_restore_vf_rebar_state(dev); > sriov_restore_state(dev); > + } > } > > /** > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h > index b81e99cd4b62a..adc54bb2c8b34 100644 > --- a/drivers/pci/pci.h > +++ b/drivers/pci/pci.h > @@ -482,6 +482,7 @@ struct pci_sriov { > u16 subsystem_vendor; /* VF subsystem vendor */ > u16 subsystem_device; /* VF subsystem device */ > resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ > + u16 vf_rebar_cap; /* VF Resizable BAR capability offset */ > bool drivers_autoprobe; /* Auto probing of VFs by driver */ > }; > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index ba326710f9c8b..bb2a334e50386 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -745,6 +745,7 @@ > #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ > #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ > #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ > +#define PCI_EXT_CAP_ID_VF_REBAR 0x24 /* VF Resizable BAR */ > #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ > #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ > #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
On Wed, 26 Mar 2025, Ilpo Järvinen wrote: > On Thu, 20 Mar 2025, Michał Winiarski wrote: > > > Similar to regular resizable BAR, VF BAR can also be resized, e.g. by > > the system firmware or the PCI subsystem itself. > > > > Add the capability ID and restore it as a part of IOV state. > > > > See PCIe r4.0, sec 9.3.7.4. > > Usually it's best o refer to latest gen doc, the section number seems to > be the same also in r6.2. Actually, it isn't. r6.2 9.3.7 does specify capability IDs so I though you be refering to that section, but there's no 9.3.7.4 section at all. -- i. > This didn't refer to spec section that specified VF Rebar ext capability > (7.8.7) though. I think it should and it would also be good to mention the > capability layout is the same as with the rebar cap. > > > Signed-off-by: Michał Winiarski <michal.winiarski@intel.com> > > Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> > > Reviewed-by: Christian König <christian.koenig@amd.com> > > --- > > drivers/pci/iov.c | 30 +++++++++++++++++++++++++++++- > > drivers/pci/pci.h | 1 + > > include/uapi/linux/pci_regs.h | 1 + > > 3 files changed, 31 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c > > index 121540f57d4bf..bf95387993cd5 100644 > > --- a/drivers/pci/iov.c > > +++ b/drivers/pci/iov.c > > @@ -7,6 +7,7 @@ > > * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com> > > */ > > > > +#include <linux/bitfield.h> > > #include <linux/pci.h> > > #include <linux/slab.h> > > #include <linux/export.h> > > @@ -830,6 +831,7 @@ static int sriov_init(struct pci_dev *dev, int pos) > > pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link); > > if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) > > iov->link = PCI_DEVFN(PCI_SLOT(dev->devfn), iov->link); > > + iov->vf_rebar_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_VF_REBAR); > > > > if (pdev) > > iov->dev = pci_dev_get(pdev); > > @@ -868,6 +870,30 @@ static void sriov_release(struct pci_dev *dev) > > dev->sriov = NULL; > > } > > > > +static void sriov_restore_vf_rebar_state(struct pci_dev *dev) > > +{ > > + unsigned int pos, nbars, i; > > + u32 ctrl; > > + > > + pos = dev->sriov->vf_rebar_cap; > > + if (!pos) > > + return; > > + > > + pci_read_config_dword(dev, pos + PCI_REBAR_CTRL, &ctrl); > > + nbars = FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); > > + > > + for (i = 0; i < nbars; i++, pos += 8) { > > + int bar_idx, size; > > + > > + pci_read_config_dword(dev, pos + PCI_REBAR_CTRL, &ctrl); > > + bar_idx = FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl); > > + size = pci_rebar_bytes_to_size(dev->sriov->barsz[bar_idx]); > > + ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; > > + ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); > > + pci_write_config_dword(dev, pos + PCI_REBAR_CTRL, ctrl); > > I started to wonder if we'd still want to have the VF Rebar ones in > uapi/linux/pci_regs.h (despite the same capability layout): > > /* > * PCI Resizable BAR and PCI VF Resizable BAR extended capabilities have > * the same layout of fields. > */ > #define PCI_VF_REBAR_CTRL PCI_REBAR_CTRL > #define PCI_VF_REBAR_CTRL_BAR_IDX PCI_REBAR_CTRL_BAR_IDX > etc. > > as then it would be possible grep to pick up only the relevant lines. > > I'd not duplicate _SHIFT defines though. FIELD_PREP/GET() in general does > not need _SHIFT defines at all and they are just duplicated information. > > > + } > > +} > > + > > static void sriov_restore_state(struct pci_dev *dev) > > { > > int i; > > @@ -1027,8 +1053,10 @@ resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno) > > */ > > void pci_restore_iov_state(struct pci_dev *dev) > > { > > - if (dev->is_physfn) > > + if (dev->is_physfn) { > > + sriov_restore_vf_rebar_state(dev); > > sriov_restore_state(dev); > > + } > > } > > > > /** > > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h > > index b81e99cd4b62a..adc54bb2c8b34 100644 > > --- a/drivers/pci/pci.h > > +++ b/drivers/pci/pci.h > > @@ -482,6 +482,7 @@ struct pci_sriov { > > u16 subsystem_vendor; /* VF subsystem vendor */ > > u16 subsystem_device; /* VF subsystem device */ > > resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ > > + u16 vf_rebar_cap; /* VF Resizable BAR capability offset */ > > bool drivers_autoprobe; /* Auto probing of VFs by driver */ > > }; > > > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > > index ba326710f9c8b..bb2a334e50386 100644 > > --- a/include/uapi/linux/pci_regs.h > > +++ b/include/uapi/linux/pci_regs.h > > @@ -745,6 +745,7 @@ > > #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ > > #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ > > #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ > > +#define PCI_EXT_CAP_ID_VF_REBAR 0x24 /* VF Resizable BAR */ > > #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ > > #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ > > #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */ > > Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> > >
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c index 121540f57d4bf..bf95387993cd5 100644 --- a/drivers/pci/iov.c +++ b/drivers/pci/iov.c @@ -7,6 +7,7 @@ * Copyright (C) 2009 Intel Corporation, Yu Zhao <yu.zhao@intel.com> */ +#include <linux/bitfield.h> #include <linux/pci.h> #include <linux/slab.h> #include <linux/export.h> @@ -830,6 +831,7 @@ static int sriov_init(struct pci_dev *dev, int pos) pci_read_config_byte(dev, pos + PCI_SRIOV_FUNC_LINK, &iov->link); if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) iov->link = PCI_DEVFN(PCI_SLOT(dev->devfn), iov->link); + iov->vf_rebar_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_VF_REBAR); if (pdev) iov->dev = pci_dev_get(pdev); @@ -868,6 +870,30 @@ static void sriov_release(struct pci_dev *dev) dev->sriov = NULL; } +static void sriov_restore_vf_rebar_state(struct pci_dev *dev) +{ + unsigned int pos, nbars, i; + u32 ctrl; + + pos = dev->sriov->vf_rebar_cap; + if (!pos) + return; + + pci_read_config_dword(dev, pos + PCI_REBAR_CTRL, &ctrl); + nbars = FIELD_GET(PCI_REBAR_CTRL_NBAR_MASK, ctrl); + + for (i = 0; i < nbars; i++, pos += 8) { + int bar_idx, size; + + pci_read_config_dword(dev, pos + PCI_REBAR_CTRL, &ctrl); + bar_idx = FIELD_GET(PCI_REBAR_CTRL_BAR_IDX, ctrl); + size = pci_rebar_bytes_to_size(dev->sriov->barsz[bar_idx]); + ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE; + ctrl |= FIELD_PREP(PCI_REBAR_CTRL_BAR_SIZE, size); + pci_write_config_dword(dev, pos + PCI_REBAR_CTRL, ctrl); + } +} + static void sriov_restore_state(struct pci_dev *dev) { int i; @@ -1027,8 +1053,10 @@ resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno) */ void pci_restore_iov_state(struct pci_dev *dev) { - if (dev->is_physfn) + if (dev->is_physfn) { + sriov_restore_vf_rebar_state(dev); sriov_restore_state(dev); + } } /** diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index b81e99cd4b62a..adc54bb2c8b34 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -482,6 +482,7 @@ struct pci_sriov { u16 subsystem_vendor; /* VF subsystem vendor */ u16 subsystem_device; /* VF subsystem device */ resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ + u16 vf_rebar_cap; /* VF Resizable BAR capability offset */ bool drivers_autoprobe; /* Auto probing of VFs by driver */ }; diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index ba326710f9c8b..bb2a334e50386 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -745,6 +745,7 @@ #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ +#define PCI_EXT_CAP_ID_VF_REBAR 0x24 /* VF Resizable BAR */ #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ #define PCI_EXT_CAP_ID_NPEM 0x29 /* Native PCIe Enclosure Management */