| Message ID | 20250321114211.2185782-2-sai.krishna.musham@amd.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | Add support for PCIe RP PERST# | expand |
[AMD Official Use Only - AMD Internal Distribution Only] Hi, Typo in commit message, corrected here, I will update in v6 patch. > Add `cpm_crx` property between `cfg` and `cpm_csr` as required. Presence of this > property results in an ABI break. - Sai Krishna > -----Original Message----- > From: Sai Krishna Musham <sai.krishna.musham@amd.com> > Sent: Friday, March 21, 2025 5:12 PM > To: bhelgaas@google.com; lpieralisi@kernel.org; kw@linux.com; > manivannan.sadhasivam@linaro.org; robh@kernel.org; krzk+dt@kernel.org; > conor+dt@kernel.org; cassel@kernel.org > Cc: linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org; Simek, Michal <michal.simek@amd.com>; Gogada, Bharat > Kumar <bharat.kumar.gogada@amd.com>; Havalige, Thippeswamy > <thippeswamy.havalige@amd.com>; Musham, Sai Krishna > <sai.krishna.musham@amd.com> > Subject: [PATCH v5 1/2] dt-bindings: PCI: xilinx-cpm: Add reset-gpios for PCIe RP > PERST# > > Introduce `reset-gpios` property to enable GPIO-based control of the PCIe RP > PERST# signal, generating assert and deassert signals. > > Traditionally, the reset was managed in hardware and enabled during initialization. > With this patch set, the reset will be handled by the driver. Consequently, the `reset- > gpios` property must be explicitly provided to ensure proper functionality. > > Add CPM clock and reset control registers base (`cpm_crx`) to handle PCIe IP reset > along with PCIe RP PERST# to avoid Link Training errors. > > Add `cpm_crx` property between `cfg` and `cpm_csr` as required. Presence of this > property results in an ABI break. > > Signed-off-by: Sai Krishna Musham <sai.krishna.musham@amd.com> > --- > Changes for v5: > - Remove `reset-gpios` property from required as it is already present > in pci-bus-common.yaml > - Update commit message > Changes for v4: > - Add CPM clock and reset control registers base to handle PCIe IP > reset. > - Update commit message. > > Changes for v3: > - None > > Changes for v2: > - Add define from include/dt-bindings/gpio/gpio.h for PERST# polarity > - Update commit message > --- > .../bindings/pci/xilinx-versal-cpm.yaml | 17 ++++++++++++----- > 1 file changed, 12 insertions(+), 5 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > index d674a24c8ccc..293df91d4e74 100644 > --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > @@ -24,15 +24,17 @@ properties: > items: > - description: CPM system level control and status registers. > - description: Configuration space region and bridge registers. > + - description: CPM clock and reset control registers. > - description: CPM5 control and status registers. > - minItems: 2 > + minItems: 3 > > reg-names: > items: > - const: cpm_slcr > - const: cfg > + - const: cpm_crx > - const: cpm_csr > - minItems: 2 > + minItems: 3 > > interrupts: > maxItems: 1 > @@ -76,6 +78,7 @@ unevaluatedProperties: false > > examples: > - | > + #include <dt-bindings/gpio/gpio.h> > > versal { > #address-cells = <2>; > @@ -98,8 +101,10 @@ examples: > <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 > 0x80000000>; > msi-map = <0x0 &its_gic 0x0 0x10000>; > reg = <0x0 0xfca10000 0x0 0x1000>, > - <0x6 0x00000000 0x0 0x10000000>; > - reg-names = "cpm_slcr", "cfg"; > + <0x6 0x00000000 0x0 0x10000000>, > + <0x0 0xfca00000 0x0 10000>; > + reg-names = "cpm_slcr", "cfg", "cpm_crx"; > + reset-gpios = <&gpio1 38 GPIO_ACTIVE_LOW>; > pcie_intc_0: interrupt-controller { > #address-cells = <0>; > #interrupt-cells = <1>; @@ -126,8 +131,10 @@ examples: > msi-map = <0x0 &its_gic 0x0 0x10000>; > reg = <0x00 0xfcdd0000 0x00 0x1000>, > <0x06 0x00000000 0x00 0x1000000>, > + <0x00 0xfcdc0000 0x00 0x10000>, > <0x00 0xfce20000 0x00 0x1000000>; > - reg-names = "cpm_slcr", "cfg", "cpm_csr"; > + reg-names = "cpm_slcr", "cfg", "cpm_crx", "cpm_csr"; > + reset-gpios = <&gpio1 38 GPIO_ACTIVE_LOW>; > > pcie_intc_1: interrupt-controller { > #address-cells = <0>; > -- > 2.44.1
On Fri, Mar 21, 2025 at 05:12:10PM +0530, Sai Krishna Musham wrote: > Introduce `reset-gpios` property to enable GPIO-based control of > the PCIe RP PERST# signal, generating assert and deassert signals. > > Traditionally, the reset was managed in hardware and enabled during > initialization. With this patch set, the reset will be handled by the > driver. Consequently, the `reset-gpios` property must be explicitly > provided to ensure proper functionality. > > Add CPM clock and reset control registers base (`cpm_crx`) to handle > PCIe IP reset along with PCIe RP PERST# to avoid Link Training errors. > > Add `cpm_crx` property between `cfg` and `cpm_csr` as required. Absence > of this property results in an ABI break. > > Signed-off-by: Sai Krishna Musham <sai.krishna.musham@amd.com> > --- > Changes for v5: > - Remove `reset-gpios` property from required as it is already present > in pci-bus-common.yaml > - Update commit message > Changes for v4: > - Add CPM clock and reset control registers base to handle PCIe IP > reset. > - Update commit message. > > Changes for v3: > - None > > Changes for v2: > - Add define from include/dt-bindings/gpio/gpio.h for PERST# polarity > - Update commit message > --- > .../bindings/pci/xilinx-versal-cpm.yaml | 17 ++++++++++++----- > 1 file changed, 12 insertions(+), 5 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > index d674a24c8ccc..293df91d4e74 100644 > --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml > @@ -24,15 +24,17 @@ properties: > items: > - description: CPM system level control and status registers. > - description: Configuration space region and bridge registers. > + - description: CPM clock and reset control registers. Nothing improved. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml index d674a24c8ccc..293df91d4e74 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml @@ -24,15 +24,17 @@ properties: items: - description: CPM system level control and status registers. - description: Configuration space region and bridge registers. + - description: CPM clock and reset control registers. - description: CPM5 control and status registers. - minItems: 2 + minItems: 3 reg-names: items: - const: cpm_slcr - const: cfg + - const: cpm_crx - const: cpm_csr - minItems: 2 + minItems: 3 interrupts: maxItems: 1 @@ -76,6 +78,7 @@ unevaluatedProperties: false examples: - | + #include <dt-bindings/gpio/gpio.h> versal { #address-cells = <2>; @@ -98,8 +101,10 @@ examples: <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>; msi-map = <0x0 &its_gic 0x0 0x10000>; reg = <0x0 0xfca10000 0x0 0x1000>, - <0x6 0x00000000 0x0 0x10000000>; - reg-names = "cpm_slcr", "cfg"; + <0x6 0x00000000 0x0 0x10000000>, + <0x0 0xfca00000 0x0 10000>; + reg-names = "cpm_slcr", "cfg", "cpm_crx"; + reset-gpios = <&gpio1 38 GPIO_ACTIVE_LOW>; pcie_intc_0: interrupt-controller { #address-cells = <0>; #interrupt-cells = <1>; @@ -126,8 +131,10 @@ examples: msi-map = <0x0 &its_gic 0x0 0x10000>; reg = <0x00 0xfcdd0000 0x00 0x1000>, <0x06 0x00000000 0x00 0x1000000>, + <0x00 0xfcdc0000 0x00 0x10000>, <0x00 0xfce20000 0x00 0x1000000>; - reg-names = "cpm_slcr", "cfg", "cpm_csr"; + reg-names = "cpm_slcr", "cfg", "cpm_crx", "cpm_csr"; + reset-gpios = <&gpio1 38 GPIO_ACTIVE_LOW>; pcie_intc_1: interrupt-controller { #address-cells = <0>;
Introduce `reset-gpios` property to enable GPIO-based control of the PCIe RP PERST# signal, generating assert and deassert signals. Traditionally, the reset was managed in hardware and enabled during initialization. With this patch set, the reset will be handled by the driver. Consequently, the `reset-gpios` property must be explicitly provided to ensure proper functionality. Add CPM clock and reset control registers base (`cpm_crx`) to handle PCIe IP reset along with PCIe RP PERST# to avoid Link Training errors. Add `cpm_crx` property between `cfg` and `cpm_csr` as required. Absence of this property results in an ABI break. Signed-off-by: Sai Krishna Musham <sai.krishna.musham@amd.com> --- Changes for v5: - Remove `reset-gpios` property from required as it is already present in pci-bus-common.yaml - Update commit message Changes for v4: - Add CPM clock and reset control registers base to handle PCIe IP reset. - Update commit message. Changes for v3: - None Changes for v2: - Add define from include/dt-bindings/gpio/gpio.h for PERST# polarity - Update commit message --- .../bindings/pci/xilinx-versal-cpm.yaml | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-)