| Message ID | 20250326075915.4073725-5-hongxing.zhu@nxp.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Krzysztof Wilczyński |
| Headers | show |
| Series | Add some enhancements for i.MX95 PCIe | expand |
On Wed, Mar 26, 2025 at 03:59:13PM +0800, Richard Zhu wrote: > ERR051586: Compliance with 8GT/s Receiver Impedance ECN. > > The default value of GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] is 1 which > makes receiver non-compliant with the ZRX-DC parameter for 2.5 GT/s when > operating at 8 GT/s or higher. It causes unnecessary timeout in L1. > > Workaround: Program GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] to 0. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > --- > drivers/pci/controller/dwc/pci-imx6.c | 33 +++++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index fbab5a4621aa..42683d6be9f2 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -1261,6 +1261,37 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp) > regulator_disable(imx_pcie->vpcie); > } > > +static void imx_pcie_host_post_init(struct dw_pcie_rp *pp) > +{ > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + struct imx_pcie *imx_pcie = to_imx_pcie(pci); > + u32 val; > + > + switch (imx_pcie->drvdata->variant) { > + case IMX95: > + case IMX95_EP: Use quirk flags if (imx_pcie->drvdata->flags & IMX6_8GT_ECN_51586 ) { ... } Frank > + /* > + * ERR051586: Compliance with 8GT/s Receiver Impedance ECN > + * > + * The default value of GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] > + * is 1 which makes receiver non-compliant with the ZRX-DC > + * parameter for 2.5 GT/s when operating at 8 GT/s or higher. > + * It causes unnecessary timeout in L1. > + * > + * Workaround: Program GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] > + * to 0. > + */ > + dw_pcie_dbi_ro_wr_en(pci); > + val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); > + val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; > + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); > + dw_pcie_dbi_ro_wr_dis(pci); > + break; > + default: > + break; > + } > +} > + > static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) > { > struct imx_pcie *imx_pcie = to_imx_pcie(pcie); > @@ -1302,6 +1333,7 @@ static const struct dw_pcie_host_ops imx_pcie_host_ops = { > static const struct dw_pcie_host_ops imx_pcie_host_dw_pme_ops = { > .init = imx_pcie_host_init, > .deinit = imx_pcie_host_exit, > + .post_init = imx_pcie_host_post_init, > }; > > static const struct dw_pcie_ops dw_pcie_ops = { > @@ -1401,6 +1433,7 @@ static int imx_add_pcie_ep(struct imx_pcie *imx_pcie, > struct device *dev = pci->dev; > > imx_pcie_host_init(pp); > + imx_pcie_host_post_init(pp); > ep = &pci->ep; > ep->ops = &pcie_ep_ops; > > -- > 2.37.1 >
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index fbab5a4621aa..42683d6be9f2 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1261,6 +1261,37 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp) regulator_disable(imx_pcie->vpcie); } +static void imx_pcie_host_post_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct imx_pcie *imx_pcie = to_imx_pcie(pci); + u32 val; + + switch (imx_pcie->drvdata->variant) { + case IMX95: + case IMX95_EP: + /* + * ERR051586: Compliance with 8GT/s Receiver Impedance ECN + * + * The default value of GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] + * is 1 which makes receiver non-compliant with the ZRX-DC + * parameter for 2.5 GT/s when operating at 8 GT/s or higher. + * It causes unnecessary timeout in L1. + * + * Workaround: Program GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] + * to 0. + */ + dw_pcie_dbi_ro_wr_en(pci); + val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); + val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); + dw_pcie_dbi_ro_wr_dis(pci); + break; + default: + break; + } +} + static u64 imx_pcie_cpu_addr_fixup(struct dw_pcie *pcie, u64 cpu_addr) { struct imx_pcie *imx_pcie = to_imx_pcie(pcie); @@ -1302,6 +1333,7 @@ static const struct dw_pcie_host_ops imx_pcie_host_ops = { static const struct dw_pcie_host_ops imx_pcie_host_dw_pme_ops = { .init = imx_pcie_host_init, .deinit = imx_pcie_host_exit, + .post_init = imx_pcie_host_post_init, }; static const struct dw_pcie_ops dw_pcie_ops = { @@ -1401,6 +1433,7 @@ static int imx_add_pcie_ep(struct imx_pcie *imx_pcie, struct device *dev = pci->dev; imx_pcie_host_init(pp); + imx_pcie_host_post_init(pp); ep = &pci->ep; ep->ops = &pcie_ep_ops;
ERR051586: Compliance with 8GT/s Receiver Impedance ECN. The default value of GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] is 1 which makes receiver non-compliant with the ZRX-DC parameter for 2.5 GT/s when operating at 8 GT/s or higher. It causes unnecessary timeout in L1. Workaround: Program GEN3_RELATED_OFF[GEN3_ZRXDC_NONCOMPL] to 0. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> --- drivers/pci/controller/dwc/pci-imx6.c | 33 +++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)