===================================================================
@@ -41,6 +41,11 @@ static inline void print_ioh_resources(s
#define IOH_LMMIOH_LIMITU 0x118
#define IOH_LCFGBUS 0x11c
+#define IOH_VTBAR 0x180
+#define IOH_VTSIZE 0x2000 /* Fixed HW size (not programmable) */
+
+#define RANGE_NUM 16
+
static void __devinit pci_root_bus_res(struct pci_dev *dev)
{
u16 word;
@@ -50,9 +55,11 @@ static void __devinit pci_root_bus_res(s
u32 mmiol_base, mmiol_end;
u64 mmioh_base, mmioh_end;
int bus_base, bus_end;
+ struct range range[RANGE_NUM];
+ int i;
/* some sys doesn't get mmconf enabled */
- if (dev->cfg_size < 0x120)
+ if (dev->cfg_size < 0x200)
return;
if (pci_root_num >= PCI_ROOT_NR) {
@@ -78,7 +85,25 @@ static void __devinit pci_root_bus_res(s
pci_read_config_dword(dev, IOH_LMMIOL, &dword);
mmiol_base = (dword & 0xff00) << (24 - 8);
mmiol_end = (dword & 0xff000000) | 0xffffff;
- update_res(info, mmiol_base, mmiol_end, IORESOURCE_MEM, 0);
+ memset(range, 0, sizeof(range));
+ add_range(range, RANGE_NUM, 0, mmiol_base, (u64)mmiol_end + 1);
+ pci_read_config_dword(dev, IOH_VTBAR, &dword);
+ if (dword & 0x1) {
+ u32 vt_base, vt_end;
+
+ vt_base = dword & 0xfffffffe;
+ vt_end = vt_base + IOH_VTSIZE - 1;
+
+ subtract_range(range, RANGE_NUM, vt_base, vt_end + 1);
+ }
+ for (i = 0; i < RANGE_NUM; i++) {
+ if (!range[i].end)
+ continue;
+
+ update_res(info, cap_resource(range[i].start),
+ cap_resource(range[i].end - 1),
+ IORESOURCE_MEM, 0);
+ }
pci_read_config_dword(dev, IOH_LMMIOH, &dword);
mmioh_base = ((u64)(dword & 0xfc00)) << (26 - 10);