@@ -449,15 +449,15 @@
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
LnkCap: Port #8, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <16us
ClockPM- Surprise- LLActRep+ BwNot-
- LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk-
+ LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
- LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+
Slot #7, PowerLimit 10.000W; Interlock- NoCompl+
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
- Changed: MRL- PresDet- LinkState-
+ SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
+ Changed: MRL- PresDet+ LinkState+
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
@@ -480,7 +480,7 @@
20: c0 f6 c0 f7 01 f0 01 f1 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 04 10 00
40: 10 80 42 01 00 80 00 00 00 00 10 00 12 4c 12 08
-50: 02 00 01 10 60 b2 3c 00 00 00 00 00 00 00 00 00
+50: 03 00 11 30 60 b2 3c 00 00 00 48 01 00 00 00 00
60: 00 00 00 00 16 00 00 00 00 00 00 00 00 00 00 00
70: 01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00
@@ -488,7 +488,7 @@
a0: 01 00 02 c8 03 01 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-d0: 00 00 00 01 02 0b 00 00 02 80 11 c1 00 00 00 00
+d0: 00 00 00 01 02 0b 00 00 02 80 11 c1 00 00 00 40
e0: 00 03 00 00 00 00 00 00 01 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 87 0f 05 08 00 00 00 00
@@ -457,7 +457,7 @@
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
- Changed: MRL- PresDet+ LinkState+
+ Changed: MRL- PresDet- LinkState+
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
@@ -480,7 +480,7 @@
20: c0 f6 c0 f7 01 f0 01 f1 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 04 10 00
40: 10 80 42 01 00 80 00 00 00 00 10 00 12 4c 12 08
-50: 03 00 11 30 60 b2 3c 00 00 00 48 01 00 00 00 00
+50: 03 00 11 30 60 b2 3c 00 00 00 40 01 00 00 00 00
60: 00 00 00 00 16 00 00 00 00 00 00 00 00 00 00 00
70: 01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00
@@ -488,7 +488,7 @@
a0: 01 00 02 c8 03 01 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-d0: 00 00 00 01 02 0b 00 00 02 80 11 c1 00 00 00 40
+d0: 00 00 00 01 02 0b 00 00 02 80 11 c1 00 00 00 00
e0: 00 03 00 00 00 00 00 00 01 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 87 0f 05 08 00 00 00 00
>
>
> Similarly, a partially detected eject of the card:
>
> 23:46:13 SlotStatus 0140
> 23:46:14 SlotStatus 0140
> 23:46:15 SlotStatus 0140
> 23:46:16 SlotStatus 0100
> 23:46:17 SlotStatus 0100
> 23:46:18 SlotStatus 0100
>
>
> --- lspci_loop.23:46:15 2013-03-11 23:46:15.000000000 +0100
> +++ lspci_loop.23:46:16 2013-03-11 23:46:16.000000000 +0100
> @@ -449,14 +449,14 @@
> DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
> LnkCap: Port #8, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <16us
> ClockPM- Surprise- LLActRep+ BwNot-
> - LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk-
> + LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk-
> ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
> - LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
> + LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt+ ABWMgmt-
> SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+
> Slot #7, PowerLimit 10.000W; Interlock- NoCompl+
> SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
> Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
> - SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
> + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
> Changed: MRL- PresDet- LinkState+
> RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
> RootCap: CRSVisible-
> @@ -480,7 +480,7 @@
> 20: c0 f6 c0 f7 01 f0 01 f1 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 04 10 00
> 40: 10 80 42 01 00 80 00 00 00 00 11 00 12 4c 12 08
> -50: 03 00 11 70 60 b2 3c 00 00 00 40 01 00 00 00 00
> +50: 02 00 11 50 60 b2 3c 00 00 00 00 01 00 00 00 00
> 60: 00 00 00 00 16 00 00 00 00 00 00 00 00 00 00 00
> 70: 01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Dtto partial hotplug eject on a system cold-booted with an empty express card slot:
23:50:03 SlotStatus 0140
23:50:04 SlotStatus 0140
23:50:05 SlotStatus 0140
23:50:07 SlotStatus 0100
23:50:08 SlotStatus 0100
23:50:09 SlotStatus 0100
@@ -446,17 +446,17 @@
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
MaxPayload 128 bytes, MaxReadReq 128 bytes
- DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
+ DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
LnkCap: Port #8, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <16us
ClockPM- Surprise- LLActRep+ BwNot-
- LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk-
+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
+ LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+
Slot #7, PowerLimit 10.000W; Interlock- NoCompl+
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
+ SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
Changed: MRL- PresDet- LinkState+
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
RootCap: CRSVisible-
@@ -479,8 +479,8 @@
10: 00 00 00 00 00 00 00 00 00 11 16 00 c0 d0 00 00
20: c0 f6 c0 f7 01 f0 01 f1 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 04 10 00
-40: 10 80 42 01 00 80 00 00 00 00 10 00 12 4c 12 08
-50: 03 00 11 30 60 b2 3c 00 00 00 40 01 00 00 00 00
+40: 10 80 42 01 00 80 00 00 00 00 11 00 12 4c 12 08
+50: 02 00 11 10 60 b2 3c 00 00 00 00 01 00 00 00 00
60: 00 00 00 00 16 00 00 00 00 00 00 00 00 00 00 00
70: 01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00
>
>
> Again, a partially detect hotplug insert:
>
> 23:46:25 SlotStatus 0100
> 23:46:26 SlotStatus 0100
> 23:46:27 SlotStatus 0100
> 23:46:29 SlotStatus 0148
> 23:46:31 SlotStatus 0140
> 23:46:32 SlotStatus 0140
> 23:46:33 SlotStatus 0140
>
>
> --- lspci_loop.23:46:27 2013-03-11 23:46:27.000000000 +0100
> +++ lspci_loop.23:46:29 2013-03-11 23:46:30.000000000 +0100
> @@ -449,15 +449,15 @@
> DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
> LnkCap: Port #8, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <16us
> ClockPM- Surprise- LLActRep+ BwNot-
> - LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk-
> + LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk-
> ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
> - LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt+ ABWMgmt-
> + LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt-
> SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+
> Slot #7, PowerLimit 10.000W; Interlock- NoCompl+
> SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
> Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
> - SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
> - Changed: MRL- PresDet- LinkState+
> + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
> + Changed: MRL- PresDet+ LinkState+
> RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
> RootCap: CRSVisible-
> RootSta: PME ReqID 0000, PMEStatus- PMEPending-
> @@ -480,7 +480,7 @@
> 20: c0 f6 c0 f7 01 f0 01 f1 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 04 10 00
> 40: 10 80 42 01 00 80 00 00 00 00 11 00 12 4c 12 08
> -50: 02 00 11 50 60 b2 3c 00 00 00 00 01 00 00 00 00
> +50: 03 00 11 70 60 b2 3c 00 00 00 48 01 00 00 00 00
> 60: 00 00 00 00 16 00 00 00 00 00 00 00 00 00 00 00
> 70: 01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> @@ -488,7 +488,7 @@
> a0: 01 00 02 c8 03 01 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> -d0: 00 00 00 01 02 0b 00 00 02 80 11 c1 00 00 00 00
> +d0: 00 00 00 01 02 0b 00 00 02 80 11 c1 00 00 00 40
> e0: 00 03 00 00 00 00 00 00 01 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 87 0f 05 08 00 00 00 00
> --- lspci_loop.23:46:29 2013-03-11 23:46:30.000000000 +0100
> +++ lspci_loop.23:46:31 2013-03-11 23:46:31.000000000 +0100
> @@ -457,7 +457,7 @@
> SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
> Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
> SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
> - Changed: MRL- PresDet+ LinkState+
> + Changed: MRL- PresDet- LinkState+
> RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
> RootCap: CRSVisible-
> RootSta: PME ReqID 0000, PMEStatus- PMEPending-
> @@ -480,7 +480,7 @@
> 20: c0 f6 c0 f7 01 f0 01 f1 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 04 10 00
> 40: 10 80 42 01 00 80 00 00 00 00 11 00 12 4c 12 08
> -50: 03 00 11 70 60 b2 3c 00 00 00 48 01 00 00 00 00
> +50: 03 00 11 70 60 b2 3c 00 00 00 40 01 00 00 00 00
> 60: 00 00 00 00 16 00 00 00 00 00 00 00 00 00 00 00
> 70: 01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> @@ -488,7 +488,7 @@
> a0: 01 00 02 c8 03 01 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> -d0: 00 00 00 01 02 0b 00 00 02 80 11 c1 00 00 00 40
> +d0: 00 00 00 01 02 0b 00 00 02 80 11 c1 00 00 00 00
> e0: 00 03 00 00 00 00 00 00 01 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 87 0f 05 08 00 00 00 00
Dtto partial hotplug insert on a system cold-booted with an empty express card slot:
23:50:15 SlotStatus 0100
23:50:16 SlotStatus 0100
23:50:17 SlotStatus 0100
23:50:19 SlotStatus 0148
23:50:20 SlotStatus 0140
23:50:21 SlotStatus 0140
23:50:22 SlotStatus 0140
@@ -449,15 +449,15 @@
DevSta: CorrErr+ UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend-
LnkCap: Port #8, Speed 5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <16us
ClockPM- Surprise- LLActRep+ BwNot-
- LnkCtl: ASPM L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk-
+ LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
- LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
+ LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt-
SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+
Slot #7, PowerLimit 10.000W; Interlock- NoCompl+
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
- SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock-
- Changed: MRL- PresDet- LinkState+
+ SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
+ Changed: MRL- PresDet+ LinkState+
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
@@ -480,7 +480,7 @@
20: c0 f6 c0 f7 01 f0 01 f1 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 04 10 00
40: 10 80 42 01 00 80 00 00 00 00 11 00 12 4c 12 08
-50: 02 00 11 10 60 b2 3c 00 00 00 00 01 00 00 00 00
+50: 03 00 11 30 60 b2 3c 00 00 00 48 01 00 00 00 00
60: 00 00 00 00 16 00 00 00 00 00 00 00 00 00 00 00
70: 01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00
@@ -488,7 +488,7 @@
a0: 01 00 02 c8 03 01 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-d0: 00 00 00 01 02 0b 00 00 02 80 11 c1 00 00 00 00
+d0: 00 00 00 01 02 0b 00 00 02 80 11 c1 00 00 00 40
e0: 00 03 00 00 00 00 00 00 01 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 87 0f 05 08 00 00 00 00
@@ -457,7 +457,7 @@
SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
- Changed: MRL- PresDet+ LinkState+
+ Changed: MRL- PresDet- LinkState+
RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
RootCap: CRSVisible-
RootSta: PME ReqID 0000, PMEStatus- PMEPending-
@@ -480,7 +480,7 @@
20: c0 f6 c0 f7 01 f0 01 f1 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 04 10 00
40: 10 80 42 01 00 80 00 00 00 00 11 00 12 4c 12 08
-50: 03 00 11 30 60 b2 3c 00 00 00 48 01 00 00 00 00
+50: 03 00 11 30 60 b2 3c 00 00 00 40 01 00 00 00 00
60: 00 00 00 00 16 00 00 00 00 00 00 00 00 00 00 00
70: 01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 05 90 00 00 00 00 00 00 00 00 00 00 00 00 00 00
@@ -488,7 +488,7 @@
a0: 01 00 02 c8 03 01 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-d0: 00 00 00 01 02 0b 00 00 02 80 11 c1 00 00 00 40
+d0: 00 00 00 01 02 0b 00 00 02 80 11 c1 00 00 00 00
e0: 00 03 00 00 00 00 00 00 01 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 87 0f 05 08 00 00 00 00