| Message ID | CAPcyv4gsXbi6Cc71wW5hob8mGuupXKkL5tHLRaZkdLZ1oAuK8Q@mail.gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 825d1508750c0cad13e5da564d47a6d59c7612d6 |
| Delegated to: | Bjorn Helgaas |
| Headers | show |
| Series | [GIT,PULL] Compute Express Linux (CXL) for v5.12-rc1 | expand |
As much as I'd love to be working on "Compute Express Linux" the subject should have read "Compute Express Link". On Tue, Feb 23, 2021 at 8:05 PM Dan Williams <dan.j.williams@intel.com> wrote: > > Hi Linus, please pull from: > > git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm tags/cxl-for-5.12 > > ...to receive an initial driver for CXL 2.0 Memory Devices. Technical > details are in the tag message and Documentation/. I am taking this > through nvdimm.git this first cycle until the cxl.git repository and > maintainer team can be set up on git.kernel.org. > > In terms of why merge this initial driver now, it establishes just > enough functionality to enumerate these devices and issue all > administrative commands. It sets a v5.12 baseline to develop the more > complicated higher order functionality like memory device > interleaving, persistent memory support, and hotplug which entangle > with ACPI, LIBNVDIMM, and PCI. > > The focus of this release is establishing the ioctl UAPI for the > management commands. Similar to NVME there are a set of standard > commands as well as the possibility for vendor specific commands. > Unlike the NVME driver the CXL driver does not enable vendor specific > command functionality by default. This conservatism is out of concern > for the fact that CXL interleaves memory across devices and implements > host memory. The system integrity implications of some commands are > more severe than NVME and vendor specific functionality is mostly > unauditable. This will be an ongoing topic of discussion with the > wider CXL community for next few months. > > The driver has been developed in the open since November against a > work-in-progress QEMU emulation of the CXL device model. That QEMU > effort has recently attracted contributions from multiple hardware > vendors. > > The driver has appeared in -next. It collected some initial static > analysis fixes and build-robot reports, but all quiet in -next for the > past week. > > A list of review tags that arrived after the branch for -next was cut > is appended to the tag message below. > > --- > > The following changes since commit 1048ba83fb1c00cd24172e23e8263972f6b5d9ac: > > Linux 5.11-rc6 (2021-01-31 13:50:09 -0800) > > are available in the Git repository at: > > git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm tags/cxl-for-5.12 > > for you to fetch changes up to 88ff5d466c0250259818f3153dbdc4af1f8615dd: > > cxl/mem: Fix potential memory leak (2021-02-22 14:44:39 -0800) > > ---------------------------------------------------------------- > cxl for 5.12 > > Introduce an initial driver for CXL 2.0 Type-3 Memory Devices. CXL is > Compute Express Link which released the 2.0 specification in November. > The Linux relevant changes in CXL 2.0 are support for an OS to > dynamically assign address space to memory devices, support for > switches, persistent memory, and hotplug. A Type-3 Memory Device is a > PCI enumerated device presenting the CXL Memory Device Class Code and > implementing the CXL.mem protocol. CXL.mem allows device to advertise > CPU and I/O coherent memory to the system, i.e. typical "System RAM" and > "Persistent Memory" in Linux /proc/iomem terms. > > In addition to the CXL.mem fast path there is an administrative command > hardware mailbox interface for maintenance and provisioning. It is this > command interface that is the focus of the initial driver. With this > driver a CXL device that is mapped by the BIOS can be administered by > Linux. Linux support for CXL PMEM and dynamic CXL address space > management are to be implemented post v5.12. > > 4cdadfd5e0a7 cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints > Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> > > 8adaf747c9f0 cxl/mem: Find device capabilities > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > b39cb1052a5c cxl/mem: Register CXL memX devices > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > 13237183c735 cxl/mem: Add a "RAW" send command > Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> > > 472b1ce6e9d6 cxl/mem: Enable commands via CEL > Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> > > 57ee605b976c cxl/mem: Add set of informational commands > Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> > > ---------------------------------------------------------------- > Ben Widawsky (7): > cxl/mem: Find device capabilities > cxl/mem: Add basic IOCTL interface > cxl/mem: Add a "RAW" send command > cxl/mem: Enable commands via CEL > cxl/mem: Add set of informational commands > MAINTAINERS: Add maintainers of the CXL driver > cxl/mem: Fix potential memory leak > > Dan Carpenter (1): > cxl/mem: Return -EFAULT if copy_to_user() fails > > Dan Williams (2): > cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints > cxl/mem: Register CXL memX devices > > .clang-format | 1 + > Documentation/ABI/testing/sysfs-bus-cxl | 26 + > Documentation/driver-api/cxl/index.rst | 12 + > Documentation/driver-api/cxl/memory-devices.rst | 46 + > Documentation/driver-api/index.rst | 1 + > Documentation/userspace-api/ioctl/ioctl-number.rst | 1 + > MAINTAINERS | 11 + > drivers/Kconfig | 1 + > drivers/Makefile | 1 + > drivers/cxl/Kconfig | 53 + > drivers/cxl/Makefile | 7 + > drivers/cxl/bus.c | 29 + > drivers/cxl/cxl.h | 95 ++ > drivers/cxl/mem.c | 1552 ++++++++++++++++++++ > drivers/cxl/pci.h | 31 + > include/linux/pci_ids.h | 1 + > include/uapi/linux/cxl_mem.h | 172 +++ > 17 files changed, 2040 insertions(+) > create mode 100644 Documentation/ABI/testing/sysfs-bus-cxl > create mode 100644 Documentation/driver-api/cxl/index.rst > create mode 100644 Documentation/driver-api/cxl/memory-devices.rst > create mode 100644 drivers/cxl/Kconfig > create mode 100644 drivers/cxl/Makefile > create mode 100644 drivers/cxl/bus.c > create mode 100644 drivers/cxl/cxl.h > create mode 100644 drivers/cxl/mem.c > create mode 100644 drivers/cxl/pci.h > create mode 100644 include/uapi/linux/cxl_mem.h
The pull request you sent on Tue, 23 Feb 2021 20:05:36 -0800:
> git://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm tags/cxl-for-5.12
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/825d1508750c0cad13e5da564d47a6d59c7612d6
Thank you!