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[7/7] PCI: cadence: Update support for TI J721e boards

Message ID CH2PPF4D26F8E1CB9C8CAE52EEB91E3CD08A2A12@CH2PPF4D26F8E1C.namprd07.prod.outlook.com (mailing list archive)
State New
Delegated to: Krzysztof Wilczyński
Headers show
Series Enhance the PCIe controller driver | expand

Commit Message

Manikandan Karunakaran Pillai March 27, 2025, 11:43 a.m. UTC 
Update the support for TI J721 boards to use the updated Cadence
PCIe controller code

Signed-off-by: Manikandan K Pillai <mpillai@cadence.com>
---
 drivers/pci/controller/cadence/pci-j721e.c | 8 ++++++++
 1 file changed, 8 insertions(+)
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Patch

diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 0341d51d6aed..118c87fb9381 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -164,6 +164,14 @@  static const struct cdns_pcie_ops j721e_pcie_ops = {
 	.start_link = j721e_pcie_start_link,
 	.stop_link = j721e_pcie_stop_link,
 	.link_up = j721e_pcie_link_up,
+	.pcie_host_init_root_port = cdns_pcie_host_init_root_port,
+	.pcie_host_bar_ib_config = cdns_pcie_host_bar_ib_config,
+	.pcie_host_init_address_translation = cdns_pcie_host_init_address_translation,
+	.pcie_detect_quiet_min_delay_set = cdns_pcie_detect_quiet_min_delay_set,
+	.pcie_set_outbound_region = cdns_pcie_set_outbound_region,
+	.pcie_set_outbound_region_for_normal_msg =
+						cdns_pcie_set_outbound_region_for_normal_msg,
+	.pcie_reset_outbound_region = cdns_pcie_reset_outbound_region,
 };
 
 static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon,