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[2/6] PCI: cadence: Add header support for PCIe next generation controllers

Message ID CH2PPF4D26F8E1CDE19710828C0186B13EEA2A42@CH2PPF4D26F8E1C.namprd07.prod.outlook.com (mailing list archive)
State New
Delegated to: Krzysztof Wilczyński
Headers show
Series [1/6] dt-bindings: pci: cadence: Add property "hpa" for PCIe controllers | expand

Commit Message

Manikandan Karunakaran Pillai March 24, 2025, 9:08 a.m. UTC 
Add the required definitions for register addresses and register bits
for the next generation Cadence PCIe controllers - High
performance architecture(HPA) controllers

Signed-off-by: Manikandan K Pillai <mpillai@cadence.com>
---
 .../controller/cadence/pcie-cadence-host.c    |  12 +-
 drivers/pci/controller/cadence/pcie-cadence.h | 290 +++++++++++++++++-
 2 files changed, 295 insertions(+), 7 deletions(-)

Comments

Hans Zhang March 24, 2025, 10:09 a.m. UTC | #1 
On 2025/3/24 17:08, Manikandan Karunakaran Pillai wrote:
> [You don't often get email from mpillai@cadence.com. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> 
> EXTERNAL EMAIL
> 
> Add the required definitions for register addresses and register bits
> for the next generation Cadence PCIe controllers - High
> performance architecture(HPA) controllers
> 
> Signed-off-by: Manikandan K Pillai <mpillai@cadence.com>
> ---
>   .../controller/cadence/pcie-cadence-host.c    |  12 +-
>   drivers/pci/controller/cadence/pcie-cadence.h | 290 +++++++++++++++++-
>   2 files changed, 295 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> index 8af95e9da7ce..1e2df49e40c6 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> @@ -175,7 +175,7 @@ static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc)
>          return ret;
>   }
> 
> -static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
> +int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
>   {
>          struct cdns_pcie *pcie = &rc->pcie;
>          u32 value, ctrl;
> @@ -215,10 +215,10 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
>          return 0;
>   }
> 
> -static int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc,
> -                                       enum cdns_pcie_rp_bar bar,
> -                                       u64 cpu_addr, u64 size,
> -                                       unsigned long flags)
> +int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc,
> +                                enum cdns_pcie_rp_bar bar,
> +                                u64 cpu_addr, u64 size,
> +                                unsigned long flags)
>   {
>          struct cdns_pcie *pcie = &rc->pcie;
>          u32 addr0, addr1, aperture, value;
> @@ -428,7 +428,7 @@ static int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc)
>          return 0;
>   }
> 
> -static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
> +int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
>   {
>          struct cdns_pcie *pcie = &rc->pcie;
>          struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rc);
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> index f5eeff834ec1..2a806e5a3685 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> @@ -218,6 +218,218 @@
>           (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \
>           CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK)
> 
> +/*
> + * High Performance Architecture(HPA) PCIe controller register
> + */
> +#define CDNS_PCIE_HPA_IP_REG_BANK              0x01000000
> +#define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK     0x01003C00
> +#define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON     0x01020000
> +/*
> + * Address Translation Registers(HPA)
> + */
> +#define CDNS_PCIE_HPA_AXI_SLAVE                 0x03000000
> +#define CDNS_PCIE_HPA_AXI_MASTER                0x03002000

Hi Manikandan,

Can you change this part of the code to look like this?

#define CDNS_PCIE_HPA_IP_REG_BANK(a)              (a)
#define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK(a)     (a)
#define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON(a)     (a)
#define CDNS_PCIE_HPA_AXI_SLAVE(a)                (a)
#define CDNS_PCIE_HPA_AXI_MASTER(a)               (a)



The offset we designed is: (Cixtech)
#define CDNS_PCIE_HPA_IP_REG_BANK 0x1000
#define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK 0x4c00
#define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON 0xf000
#define CDNS_PCIE_HPA_AXI_SLAVE 0x9000
#define CDNS_PCIE_HPA_AXI_MASTER 0xb000
#define CDNS_PCIE_HPA_AXI_HLS_REGISTERS 0xc000
#define CDNS_PCIE_HPA_DTI_REGISTERS 0xd000
#define CDNS_PCIE_HPA_AXI_RAS_REGISTERS 0xe000
#define CDNS_PCIE_HPA_DMA_BASE 0xf400
#define CDNS_PCIE_HPA_DMA_COMMON_BASE 0xf800


The original register bank consumed at least 48MB address space which is 
begin from 0x0000_0000 to 0x03020000. Because there is unoccupied 
address space between every two register banks , our hardware remaps the 
registers to a smaller address space which means the register bank 
offset address is changed by custormer. So, we cannot utilise the common 
code directly without rewriting the function.


We submit and pull a Cadence case: #46872873

We will also reply to you in the case.

Best regards,
Hans

> +/*
> + * Root port register base address
> + */
> +#define CDNS_PCIE_HPA_RP_BASE                  0x0
> +
> +#define CDNS_PCIE_HPA_LM_ID                    (CDNS_PCIE_HPA_IP_REG_BANK + 0x1420)
> +
> +/*
> + * Endpoint Function BARs(HPA) Configuration Registers
> + */
> +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn) \
> +       (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(fn) : \
> +                       CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(fn))
> +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(pfn) \
> +       (CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK  + (0x4000 * (pfn)))
> +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(pfn) \
> +       (CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK  + (0x4000 * (pfn)) + 0x04)
> +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn) \
> +       (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(fn) : \
> +                       CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(fn))
> +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(vfn) \
> +       (CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK + (0x4000 * (vfn)) + 0x08)
> +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(vfn) \
> +       (CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK + (0x4000 * (vfn)) + 0x0C)
> +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(f) \
> +       (GENMASK(9, 4) << ((f) * 10))
> +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
> +       (((a) << (4 + ((b) * 10))) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)))
> +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(f) \
> +       (GENMASK(3, 0) << ((f) * 10))
> +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \
> +       (((c) << ((b) * 10)) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)))
> +
> +/*
> + * Endpoint Function Configuration Register
> + */
> +#define CDNS_PCIE_HPA_LM_EP_FUNC_CFG           (CDNS_PCIE_HPA_IP_REG_BANK + 0x02c0)
> +
> +/*
> + * Root Complex BAR Configuration Register
> + */
> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG (CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK + 0x14)
> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK     GENMASK(9, 4)
> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE(a) \
> +       FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK, a)
> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK         GENMASK(3, 0)
> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(c) \
> +       FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK, c)
> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK     GENMASK(19, 14)
> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE(a) \
> +       FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK, a)
> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK         GENMASK(13, 10)
> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(c) \
> +       FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK, c)
> +
> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(20)
> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(21)
> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE           BIT(22)
> +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS           BIT(23)
> +
> +/* BAR control values applicable to both Endpoint Function and Root Complex */
> +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED              0x0
> +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS             0x3
> +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS            0x1
> +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS   0x9
> +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS            0x5
> +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS   0xD
> +
> +#define HPA_LM_RC_BAR_CFG_CTRL_DISABLED(bar)                \
> +               (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED << ((bar) * 10))
> +#define HPA_LM_RC_BAR_CFG_CTRL_IO_32BITS(bar)               \
> +               (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS << ((bar) * 10))
> +#define HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar)              \
> +               (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS << ((bar) * 10))
> +#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \
> +               (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << ((bar) * 10))
> +#define HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar)              \
> +               (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS << ((bar) * 10))
> +#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \
> +               (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << ((bar) * 10))
> +#define HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture)           \
> +               (((aperture) - 7) << ((bar) * 10))
> +
> +#define CDNS_PCIE_HPA_LM_PTM_CTRL              (CDNS_PCIE_HPA_IP_REG_BANK + 0x0520)
> +#define CDNS_PCIE_HPA_LM_TPM_CTRL_PTMRSEN      BIT(17)
> +
> +/*
> + * Root Port Registers PCI config space(HPA) for root port function
> + */
> +#define CDNS_PCIE_HPA_RP_CAP_OFFSET    0xC0
> +
> +/*
> + * Region r Outbound AXI to PCIe Address Translation Register 0
> + */
> +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r) \
> +       (CDNS_PCIE_HPA_AXI_SLAVE + 0x1010 + ((r) & 0x1F) * 0x0080)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK    GENMASK(5, 0)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \
> +       FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK, ((nbits) - 1))
> +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK    GENMASK(23, 16)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
> +       FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK, devfn)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK      GENMASK(31, 24)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
> +       FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK, bus)
> +
> +/*
> + * Region r Outbound AXI to PCIe Address Translation Register 1
> + */
> +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r) \
> +       (CDNS_PCIE_HPA_AXI_SLAVE + 0x1014 + ((r) & 0x1F) * 0x0080)
> +
> +/*
> + * Region r Outbound PCIe Descriptor Register 0
> + */
> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r) \
> +       (CDNS_PCIE_HPA_AXI_SLAVE + 0x1008 + ((r) & 0x1F) * 0x0080)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK         GENMASK(28, 24)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM  \
> +       FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x0)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO   \
> +       FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x2)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0  \
> +       FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x4)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1  \
> +       FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x5)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG  \
> +       FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x10)
> +
> +/*
> + * Region r Outbound PCIe Descriptor Register 1
> + */
> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r) \
> +       (CDNS_PCIE_HPA_AXI_SLAVE + 0x100C + ((r) & 0x1F) * 0x0080)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK  GENMASK(31, 24)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(bus) \
> +       FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK, bus)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK    GENMASK(23, 16)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(devfn) \
> +       FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK, devfn)
> +
> +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r) \
> +       (CDNS_PCIE_HPA_AXI_SLAVE + 0x1018 + ((r) & 0x1F) * 0x0080)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS BIT(26)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN BIT(25)
> +
> +/*
> + * Region r AXI Region Base Address Register 0
> + */
> +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r) \
> +       (CDNS_PCIE_HPA_AXI_SLAVE + 0x1000 + ((r) & 0x1F) * 0x0080)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK    GENMASK(5, 0)
> +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \
> +       FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK, ((nbits) - 1))
> +
> +/*
> + * Region r AXI Region Base Address Register 1
> + */
> +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r) \
> +       (CDNS_PCIE_HPA_AXI_SLAVE + 0x1004 + ((r) & 0x1F) * 0x0080)
> +
> +/*
> + * Root Port BAR Inbound PCIe to AXI Address Translation Register
> + */
> +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar) \
> +       (CDNS_PCIE_HPA_AXI_MASTER + ((bar) * 0x0008))
> +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK        GENMASK(5, 0)
> +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \
> +       FIELD_PREP(CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK, ((nbits) - 1))
> +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar) \
> +       (CDNS_PCIE_HPA_AXI_MASTER + 0x04 + ((bar) * 0x0008))
> +
> +/*
> + * AXI link down register
> + */
> +#define CDNS_PCIE_HPA_AT_LINKDOWN (CDNS_PCIE_HPA_AXI_SLAVE + 0x04)
> +
> +/*
> + * Physical Layer Configuration Register 0
> + * This register contains the parameters required for functional setup
> + * of Physical Layer.
> + */
> +#define CDNS_PCIE_HPA_PHY_LAYER_CFG0     (CDNS_PCIE_HPA_IP_REG_BANK + 0x0400)
> +#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK  GENMASK(26, 24)
> +#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay) \
> +       FIELD_PREP(CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK, delay)
> +#define CDNS_PCIE_HPA_LINK_TRNG_EN_MASK  GENMASK(27, 27)
> +
> +#define CDNS_PCIE_HPA_PHY_DBG_STS_REG0   (CDNS_PCIE_HPA_IP_REG_BANK + 0x0420)
> +
> +#define CDNS_PCIE_HPA_RP_MAX_IB     0x3
> +#define CDNS_PCIE_HPA_MAX_OB        15
> +
> +/*
> + * Endpoint Function BAR Inbound PCIe to AXI Address Translation Register(HPA)
> + */
> +#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \
> +       (CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON + ((fn) * 0x0040) + ((bar) * 0x0008))
> +#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \
> +       (CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON + 0x4 + ((fn) * 0x0040) + ((bar) * 0x0008))
> +
>   enum cdns_pcie_rp_bar {
>          RP_BAR_UNDEFINED = -1,
>          RP_BAR0,
> @@ -249,6 +461,7 @@ struct cdns_pcie_rp_ib_bar {
>   #define CDNS_PCIE_MSG_NO_DATA                  BIT(16)
> 
>   struct cdns_pcie;
> +struct cdns_pcie_rc;
> 
>   enum cdns_pcie_msg_code {
>          MSG_CODE_ASSERT_INTA    = 0x20,
> @@ -286,6 +499,20 @@ struct cdns_pcie_ops {
>          void    (*stop_link)(struct cdns_pcie *pcie);
>          bool    (*link_up)(struct cdns_pcie *pcie);
>          u64     (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr);
> +       int     (*pcie_host_init_root_port)(struct cdns_pcie_rc *rc);
> +       int     (*pcie_host_bar_ib_config)(struct cdns_pcie_rc *rc,
> +                                          enum cdns_pcie_rp_bar bar,
> +                                          u64 cpu_addr, u64 size,
> +                                          unsigned long flags);
> +       int     (*pcie_host_init_address_translation)(struct cdns_pcie_rc *rc);
> +       void    (*pcie_detect_quiet_min_delay_set)(struct cdns_pcie *pcie);
> +       void    (*pcie_set_outbound_region)(struct cdns_pcie *pcie, u8 busnr, u8 fn,
> +                                           u32 r, bool is_io, u64 cpu_addr,
> +                                           u64 pci_addr, size_t size);
> +       void    (*pcie_set_outbound_region_for_normal_msg)(struct cdns_pcie *pcie,
> +                                                          u8 busnr, u8 fn, u32 r,
> +                                                          u64 cpu_addr);
> +       void    (*pcie_reset_outbound_region)(struct cdns_pcie *pcie, u32 r);
>   };
> 
>   /**
> @@ -305,6 +532,7 @@ struct cdns_pcie {
>          struct resource         *mem_res;
>          struct device           *dev;
>          bool                    is_rc;
> +       bool                    is_hpa;
>          int                     phy_count;
>          struct phy              **phy;
>          struct device_link      **link;
> @@ -444,6 +672,8 @@ static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie,
>   {
>          void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
> 
> +       if (pcie->is_hpa)
> +               addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg;
>          cdns_pcie_write_sz(addr, 0x1, value);
>   }
> 
> @@ -452,6 +682,8 @@ static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie,
>   {
>          void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
> 
> +       if (pcie->is_hpa)
> +               addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg;
>          cdns_pcie_write_sz(addr, 0x2, value);
>   }
> 
> @@ -459,6 +691,8 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg)
>   {
>          void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
> 
> +       if (pcie->is_hpa)
> +               addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg;
>          return cdns_pcie_read_sz(addr, 0x2);
>   }
> 
> @@ -525,6 +759,22 @@ int cdns_pcie_host_init(struct cdns_pcie_rc *rc);
>   int cdns_pcie_host_setup(struct cdns_pcie_rc *rc);
>   void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
>                                 int where);
> +int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc);
> +int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc,
> +                                enum cdns_pcie_rp_bar bar,
> +                                u64 cpu_addr, u64 size,
> +                                unsigned long flags);
> +int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc);
> +int cdns_pcie_host_init(struct cdns_pcie_rc *rc);
> +void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn, int where);
> +int cdns_pcie_hpa_host_init_root_port(struct cdns_pcie_rc *rc);
> +int cdns_pcie_hpa_host_bar_ib_config(struct cdns_pcie_rc *rc,
> +                                    enum cdns_pcie_rp_bar bar,
> +                                    u64 cpu_addr, u64 size,
> +                                    unsigned long flags);
> +int cdns_pcie_hpa_host_init_address_translation(struct cdns_pcie_rc *rc);
> +int cdns_pcie_hpa_host_init(struct cdns_pcie_rc *rc);
> +
>   #else
>   static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc)
>   {
> @@ -546,6 +796,34 @@ static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int d
>   {
>          return NULL;
>   }
> +
> +void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
> +{
> +       return NULL;
> +}
> +
> +int cdns_pcie_hpa_host_init_root_port(struct cdns_pcie_rc *rc)
> +{
> +       return 0;
> +}
> +
> +int cdns_pcie_hpa_host_bar_ib_config(struct cdns_pcie_rc *rc,
> +                                    enum cdns_pcie_rp_bar bar,
> +                                    u64 cpu_addr, u64 size,
> +                                    unsigned long flags)
> +{
> +       return 0;
> +}
> +
> +int cdns_pcie_hpa_host_init_address_translation(struct cdns_pcie_rc *rc)
> +{
> +       return 0;
> +}
> +
> +int cdns_pcie_hpa_host_init(struct cdns_pcie_rc *rc)
> +{
> +       return 0;
> +}
>   #endif
> 
>   #ifdef CONFIG_PCIE_CADENCE_EP
> @@ -556,7 +834,10 @@ static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
>          return 0;
>   }
>   #endif
> -
> +bool cdns_pcie_linkup(struct cdns_pcie *pcie);
> +bool cdns_pcie_hpa_linkup(struct cdns_pcie *pcie);
> +int cdns_pcie_hpa_startlink(struct cdns_pcie *pcie);
> +void cdns_pcie_hpa_stop_link(struct cdns_pcie *pcie);
>   void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie);
> 
>   void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
> @@ -571,6 +852,13 @@ void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
>   void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
>   int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
>   int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
> +void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie);
> +void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
> +                                      u32 r, bool is_io, u64 cpu_addr, u64 pci_addr, size_t size);
> +void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
> +                                                     u8 busnr, u8 fn, u32 r, u64 cpu_addr);
> +void cdns_pcie_hpa_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
> +
>   extern const struct dev_pm_ops cdns_pcie_pm_ops;
> 
>   #endif /* _PCIE_CADENCE_H */
> --
> 2.27.0
> 
>
Hans Zhang March 25, 2025, 3:12 a.m. UTC | #2 
On 2025/3/24 18:09, hans.zhang wrote:
>> + * High Performance Architecture(HPA) PCIe controller register
>> + */
>> +#define CDNS_PCIE_HPA_IP_REG_BANK              0x01000000
>> +#define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK     0x01003C00
>> +#define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON     0x01020000
>> +/*
>> + * Address Translation Registers(HPA)
>> + */
>> +#define CDNS_PCIE_HPA_AXI_SLAVE                 0x03000000
>> +#define CDNS_PCIE_HPA_AXI_MASTER                0x03002000
> 
> Hi Manikandan,
> 
> Can you change this part of the code to look like this?
> 
> #define CDNS_PCIE_HPA_IP_REG_BANK(a)              (a)
> #define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK(a)     (a)
> #define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON(a)     (a)
> #define CDNS_PCIE_HPA_AXI_SLAVE(a)                (a)
> #define CDNS_PCIE_HPA_AXI_MASTER(a)               (a)
> 
> 
> 
> The offset we designed is: (Cixtech)
> #define CDNS_PCIE_HPA_IP_REG_BANK 0x1000
> #define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK 0x4c00
> #define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON 0xf000
> #define CDNS_PCIE_HPA_AXI_SLAVE 0x9000
> #define CDNS_PCIE_HPA_AXI_MASTER 0xb000
> #define CDNS_PCIE_HPA_AXI_HLS_REGISTERS 0xc000
> #define CDNS_PCIE_HPA_DTI_REGISTERS 0xd000
> #define CDNS_PCIE_HPA_AXI_RAS_REGISTERS 0xe000
> #define CDNS_PCIE_HPA_DMA_BASE 0xf400
> #define CDNS_PCIE_HPA_DMA_COMMON_BASE 0xf800
> 
> 
> The original register bank consumed at least 48MB address space which is 
> begin from 0x0000_0000 to 0x03020000. Because there is unoccupied 
> address space between every two register banks , our hardware remaps the 
> registers to a smaller address space which means the register bank 
> offset address is changed by custormer. So, we cannot utilise the common 
> code directly without rewriting the function.
> 
> 
> We submit and pull a Cadence case: #46872873
> 
> We will also reply to you in the case.

Reply from Cadence case Manikandan:
Another option I can propose is to pass these values through the DTS 
file … (Hopefully that would be lesser changes)

Hans:
I agree to get it through the DTS attribute, please modify it, so as to 
be more flexible. This offset value may be modified when RTL is integrated.

Best regards,
Hans
diff mbox series

Patch

diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index 8af95e9da7ce..1e2df49e40c6 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -175,7 +175,7 @@  static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc)
 	return ret;
 }
 
-static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
+int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
 {
 	struct cdns_pcie *pcie = &rc->pcie;
 	u32 value, ctrl;
@@ -215,10 +215,10 @@  static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
 	return 0;
 }
 
-static int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc,
-					enum cdns_pcie_rp_bar bar,
-					u64 cpu_addr, u64 size,
-					unsigned long flags)
+int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc,
+				 enum cdns_pcie_rp_bar bar,
+				 u64 cpu_addr, u64 size,
+				 unsigned long flags)
 {
 	struct cdns_pcie *pcie = &rc->pcie;
 	u32 addr0, addr1, aperture, value;
@@ -428,7 +428,7 @@  static int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc)
 	return 0;
 }
 
-static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
+int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
 {
 	struct cdns_pcie *pcie = &rc->pcie;
 	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(rc);
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index f5eeff834ec1..2a806e5a3685 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -218,6 +218,218 @@ 
 	 (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \
 	 CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK)
 
+/*
+ * High Performance Architecture(HPA) PCIe controller register
+ */
+#define CDNS_PCIE_HPA_IP_REG_BANK		0x01000000
+#define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK	0x01003C00
+#define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON	0x01020000
+/*
+ * Address Translation Registers(HPA)
+ */
+#define CDNS_PCIE_HPA_AXI_SLAVE                 0x03000000
+#define CDNS_PCIE_HPA_AXI_MASTER                0x03002000
+/*
+ * Root port register base address
+ */
+#define CDNS_PCIE_HPA_RP_BASE			0x0
+
+#define CDNS_PCIE_HPA_LM_ID			(CDNS_PCIE_HPA_IP_REG_BANK + 0x1420)
+
+/*
+ * Endpoint Function BARs(HPA) Configuration Registers
+ */
+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn) \
+	(((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(fn) : \
+			CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(fn))
+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(pfn) \
+	(CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK  + (0x4000 * (pfn)))
+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(pfn) \
+	(CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK  + (0x4000 * (pfn)) + 0x04)
+#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn) \
+	(((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(fn) : \
+			CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(fn))
+#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(vfn) \
+	(CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK + (0x4000 * (vfn)) + 0x08)
+#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(vfn) \
+	(CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK + (0x4000 * (vfn)) + 0x0C)
+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(f) \
+	(GENMASK(9, 4) << ((f) * 10))
+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
+	(((a) << (4 + ((b) * 10))) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)))
+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(f) \
+	(GENMASK(3, 0) << ((f) * 10))
+#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \
+	(((c) << ((b) * 10)) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)))
+
+/*
+ * Endpoint Function Configuration Register
+ */
+#define CDNS_PCIE_HPA_LM_EP_FUNC_CFG		(CDNS_PCIE_HPA_IP_REG_BANK + 0x02c0)
+
+/*
+ * Root Complex BAR Configuration Register
+ */
+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG (CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK + 0x14)
+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK     GENMASK(9, 4)
+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE(a) \
+	FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK, a)
+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK         GENMASK(3, 0)
+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(c) \
+	FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK, c)
+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK     GENMASK(19, 14)
+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE(a) \
+	FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK, a)
+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK         GENMASK(13, 10)
+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(c) \
+	FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK, c)
+
+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(20)
+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(21)
+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE           BIT(22)
+#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS           BIT(23)
+
+/* BAR control values applicable to both Endpoint Function and Root Complex */
+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED              0x0
+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS             0x3
+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS            0x1
+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS   0x9
+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS            0x5
+#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS   0xD
+
+#define HPA_LM_RC_BAR_CFG_CTRL_DISABLED(bar)                \
+		(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED << ((bar) * 10))
+#define HPA_LM_RC_BAR_CFG_CTRL_IO_32BITS(bar)               \
+		(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS << ((bar) * 10))
+#define HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar)              \
+		(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS << ((bar) * 10))
+#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \
+		(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << ((bar) * 10))
+#define HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar)              \
+		(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS << ((bar) * 10))
+#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \
+		(CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << ((bar) * 10))
+#define HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture)           \
+		(((aperture) - 7) << ((bar) * 10))
+
+#define CDNS_PCIE_HPA_LM_PTM_CTRL		(CDNS_PCIE_HPA_IP_REG_BANK + 0x0520)
+#define CDNS_PCIE_HPA_LM_TPM_CTRL_PTMRSEN	BIT(17)
+
+/*
+ * Root Port Registers PCI config space(HPA) for root port function
+ */
+#define CDNS_PCIE_HPA_RP_CAP_OFFSET	0xC0
+
+/*
+ * Region r Outbound AXI to PCIe Address Translation Register 0
+ */
+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r) \
+	(CDNS_PCIE_HPA_AXI_SLAVE + 0x1010 + ((r) & 0x1F) * 0x0080)
+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK    GENMASK(5, 0)
+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \
+	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK, ((nbits) - 1))
+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK    GENMASK(23, 16)
+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
+	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK, devfn)
+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK      GENMASK(31, 24)
+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
+	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK, bus)
+
+/*
+ * Region r Outbound AXI to PCIe Address Translation Register 1
+ */
+#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r) \
+	(CDNS_PCIE_HPA_AXI_SLAVE + 0x1014 + ((r) & 0x1F) * 0x0080)
+
+/*
+ * Region r Outbound PCIe Descriptor Register 0
+ */
+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r) \
+	(CDNS_PCIE_HPA_AXI_SLAVE + 0x1008 + ((r) & 0x1F) * 0x0080)
+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK         GENMASK(28, 24)
+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM  \
+	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x0)
+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO   \
+	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x2)
+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0  \
+	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x4)
+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1  \
+	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x5)
+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG  \
+	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x10)
+
+/*
+ * Region r Outbound PCIe Descriptor Register 1
+ */
+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r) \
+	(CDNS_PCIE_HPA_AXI_SLAVE + 0x100C + ((r) & 0x1F) * 0x0080)
+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK  GENMASK(31, 24)
+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(bus) \
+	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK, bus)
+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK    GENMASK(23, 16)
+#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(devfn) \
+	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK, devfn)
+
+#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r) \
+	(CDNS_PCIE_HPA_AXI_SLAVE + 0x1018 + ((r) & 0x1F) * 0x0080)
+#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS BIT(26)
+#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN BIT(25)
+
+/*
+ * Region r AXI Region Base Address Register 0
+ */
+#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r) \
+	(CDNS_PCIE_HPA_AXI_SLAVE + 0x1000 + ((r) & 0x1F) * 0x0080)
+#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK    GENMASK(5, 0)
+#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \
+	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK, ((nbits) - 1))
+
+/*
+ * Region r AXI Region Base Address Register 1
+ */
+#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r) \
+	(CDNS_PCIE_HPA_AXI_SLAVE + 0x1004 + ((r) & 0x1F) * 0x0080)
+
+/*
+ * Root Port BAR Inbound PCIe to AXI Address Translation Register
+ */
+#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar) \
+	(CDNS_PCIE_HPA_AXI_MASTER + ((bar) * 0x0008))
+#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK        GENMASK(5, 0)
+#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \
+	FIELD_PREP(CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK, ((nbits) - 1))
+#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar) \
+	(CDNS_PCIE_HPA_AXI_MASTER + 0x04 + ((bar) * 0x0008))
+
+/*
+ * AXI link down register
+ */
+#define CDNS_PCIE_HPA_AT_LINKDOWN (CDNS_PCIE_HPA_AXI_SLAVE + 0x04)
+
+/*
+ * Physical Layer Configuration Register 0
+ * This register contains the parameters required for functional setup
+ * of Physical Layer.
+ */
+#define CDNS_PCIE_HPA_PHY_LAYER_CFG0     (CDNS_PCIE_HPA_IP_REG_BANK + 0x0400)
+#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK  GENMASK(26, 24)
+#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay) \
+	FIELD_PREP(CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK, delay)
+#define CDNS_PCIE_HPA_LINK_TRNG_EN_MASK  GENMASK(27, 27)
+
+#define CDNS_PCIE_HPA_PHY_DBG_STS_REG0   (CDNS_PCIE_HPA_IP_REG_BANK + 0x0420)
+
+#define CDNS_PCIE_HPA_RP_MAX_IB     0x3
+#define CDNS_PCIE_HPA_MAX_OB        15
+
+/*
+ * Endpoint Function BAR Inbound PCIe to AXI Address Translation Register(HPA)
+ */
+#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \
+	(CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON + ((fn) * 0x0040) + ((bar) * 0x0008))
+#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \
+	(CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON + 0x4 + ((fn) * 0x0040) + ((bar) * 0x0008))
+
 enum cdns_pcie_rp_bar {
 	RP_BAR_UNDEFINED = -1,
 	RP_BAR0,
@@ -249,6 +461,7 @@  struct cdns_pcie_rp_ib_bar {
 #define CDNS_PCIE_MSG_NO_DATA			BIT(16)
 
 struct cdns_pcie;
+struct cdns_pcie_rc;
 
 enum cdns_pcie_msg_code {
 	MSG_CODE_ASSERT_INTA	= 0x20,
@@ -286,6 +499,20 @@  struct cdns_pcie_ops {
 	void	(*stop_link)(struct cdns_pcie *pcie);
 	bool	(*link_up)(struct cdns_pcie *pcie);
 	u64     (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr);
+	int	(*pcie_host_init_root_port)(struct cdns_pcie_rc *rc);
+	int	(*pcie_host_bar_ib_config)(struct cdns_pcie_rc *rc,
+					   enum cdns_pcie_rp_bar bar,
+					   u64 cpu_addr, u64 size,
+					   unsigned long flags);
+	int	(*pcie_host_init_address_translation)(struct cdns_pcie_rc *rc);
+	void	(*pcie_detect_quiet_min_delay_set)(struct cdns_pcie *pcie);
+	void	(*pcie_set_outbound_region)(struct cdns_pcie *pcie, u8 busnr, u8 fn,
+					    u32 r, bool is_io, u64 cpu_addr,
+					    u64 pci_addr, size_t size);
+	void	(*pcie_set_outbound_region_for_normal_msg)(struct cdns_pcie *pcie,
+							   u8 busnr, u8 fn, u32 r,
+							   u64 cpu_addr);
+	void	(*pcie_reset_outbound_region)(struct cdns_pcie *pcie, u32 r);
 };
 
 /**
@@ -305,6 +532,7 @@  struct cdns_pcie {
 	struct resource		*mem_res;
 	struct device		*dev;
 	bool			is_rc;
+	bool			is_hpa;
 	int			phy_count;
 	struct phy		**phy;
 	struct device_link	**link;
@@ -444,6 +672,8 @@  static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie,
 {
 	void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
 
+	if (pcie->is_hpa)
+		addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg;
 	cdns_pcie_write_sz(addr, 0x1, value);
 }
 
@@ -452,6 +682,8 @@  static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie,
 {
 	void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
 
+	if (pcie->is_hpa)
+		addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg;
 	cdns_pcie_write_sz(addr, 0x2, value);
 }
 
@@ -459,6 +691,8 @@  static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg)
 {
 	void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
 
+	if (pcie->is_hpa)
+		addr = pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg;
 	return cdns_pcie_read_sz(addr, 0x2);
 }
 
@@ -525,6 +759,22 @@  int cdns_pcie_host_init(struct cdns_pcie_rc *rc);
 int cdns_pcie_host_setup(struct cdns_pcie_rc *rc);
 void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
 			       int where);
+int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc);
+int cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc,
+				 enum cdns_pcie_rp_bar bar,
+				 u64 cpu_addr, u64 size,
+				 unsigned long flags);
+int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc);
+int cdns_pcie_host_init(struct cdns_pcie_rc *rc);
+void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn, int where);
+int cdns_pcie_hpa_host_init_root_port(struct cdns_pcie_rc *rc);
+int cdns_pcie_hpa_host_bar_ib_config(struct cdns_pcie_rc *rc,
+				     enum cdns_pcie_rp_bar bar,
+				     u64 cpu_addr, u64 size,
+				     unsigned long flags);
+int cdns_pcie_hpa_host_init_address_translation(struct cdns_pcie_rc *rc);
+int cdns_pcie_hpa_host_init(struct cdns_pcie_rc *rc);
+
 #else
 static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc)
 {
@@ -546,6 +796,34 @@  static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int d
 {
 	return NULL;
 }
+
+void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn, int where)
+{
+	return NULL;
+}
+
+int cdns_pcie_hpa_host_init_root_port(struct cdns_pcie_rc *rc)
+{
+	return 0;
+}
+
+int cdns_pcie_hpa_host_bar_ib_config(struct cdns_pcie_rc *rc,
+				     enum cdns_pcie_rp_bar bar,
+				     u64 cpu_addr, u64 size,
+				     unsigned long flags)
+{
+	return 0;
+}
+
+int cdns_pcie_hpa_host_init_address_translation(struct cdns_pcie_rc *rc)
+{
+	return 0;
+}
+
+int cdns_pcie_hpa_host_init(struct cdns_pcie_rc *rc)
+{
+	return 0;
+}
 #endif
 
 #ifdef CONFIG_PCIE_CADENCE_EP
@@ -556,7 +834,10 @@  static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
 	return 0;
 }
 #endif
-
+bool cdns_pcie_linkup(struct cdns_pcie *pcie);
+bool cdns_pcie_hpa_linkup(struct cdns_pcie *pcie);
+int cdns_pcie_hpa_startlink(struct cdns_pcie *pcie);
+void cdns_pcie_hpa_stop_link(struct cdns_pcie *pcie);
 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie);
 
 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
@@ -571,6 +852,13 @@  void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
 void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
 int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
 int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
+void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie);
+void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
+				       u32 r, bool is_io, u64 cpu_addr, u64 pci_addr, size_t size);
+void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
+						      u8 busnr, u8 fn, u32 r, u64 cpu_addr);
+void cdns_pcie_hpa_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
+
 extern const struct dev_pm_ops cdns_pcie_pm_ops;
 
 #endif /* _PCIE_CADENCE_H */