@@ -859,6 +859,52 @@
status = "disabled";
};
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@216000000 {
+ clock-latency-ns = <2000>;
+ opp-hz = /bits/ 64 <216000000>;
+ opp-suspend;
+ };
+
+ opp@312000000 {
+ clock-latency-ns = <125000>;
+ opp-hz = /bits/ 64 <312000000>;
+ };
+
+ opp@456000000 {
+ clock-latency-ns = <125000>;
+ opp-hz = /bits/ 64 <456000000>;
+ };
+
+ opp@608000000 {
+ clock-latency-ns = <125000>;
+ opp-hz = /bits/ 64 <608000000>;
+ };
+
+ opp@760000000 {
+ clock-latency-ns = <125000>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@816000000 {
+ clock-latency-ns = <125000>;
+ opp-hz = /bits/ 64 <816000000>;
+ };
+
+ opp@912000000 {
+ clock-latency-ns = <125000>;
+ opp-hz = /bits/ 64 <912000000>;
+ };
+
+ opp@1000000000 {
+ clock-latency-ns = <125000>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -867,12 +913,24 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
+ clocks = <&tegra_car TEGRA20_CLK_PLL_X>,
+ <&tegra_car TEGRA20_CLK_PLL_P>,
+ <&tegra_car TEGRA20_CLK_CCLK>;
+ clock-names = "pll_x", "backup", "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
+ clocks = <&tegra_car TEGRA20_CLK_PLL_X>,
+ <&tegra_car TEGRA20_CLK_PLL_P>,
+ <&tegra_car TEGRA20_CLK_CCLK>;
+ clock-names = "pll_x", "backup", "cpu";
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
};
};
Add CPU's Operating Performance Points to the device tree, they are used by the CPUFreq driver and allow to setup thermal throttling for the boards by linking the cooling device (CPU) with thermal sensors via thermal-zones description. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- arch/arm/boot/dts/tegra20.dtsi | 58 ++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+)