diff mbox series

[v10,01/13] clk: samsung: add needed IDs for DMC clocks in Exynos5420

Message ID 20190614095309.24100-2-l.luba@partner.samsung.com (mailing list archive)
State Not Applicable, archived
Headers show
Series [v10,01/13] clk: samsung: add needed IDs for DMC clocks in Exynos5420 | expand

Commit Message

Lukasz Luba June 14, 2019, 9:52 a.m. UTC
Define new IDs for clocks used by Dynamic Memory Controller in
Exynos5422 SoC.

Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
 include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

Comments

Krzysztof Kozlowski June 14, 2019, 12:04 p.m. UTC | #1
On Fri, 14 Jun 2019 at 11:53, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> Define new IDs for clocks used by Dynamic Memory Controller in
> Exynos5422 SoC.
>
> Acked-by: Rob Herring <robh@kernel.org>
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
>  include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)

I do not quite understand why this patch is still being resent instead
of have been applied some time ago. Are there any issues here? Or are
there any issues with the entire patchset (except some review comments
to be resolved)? If not, then this is a dependency which should go
regardless of other patches. There is no point to keep it pending...
All other changes, e.g. DTS will have to wait for more cycles till
this gets in.

Therefore either please apply this or please comment what is stopping
dependencies from being applied.

Best regards,
Krzysztof
On 6/14/19 14:04, Krzysztof Kozlowski wrote:
> I do not quite understand why this patch is still being resent instead
> of have been applied some time ago. Are there any issues here? Or are
> there any issues with the entire patchset (except some review comments
> to be resolved)? If not, then this is a dependency which should go
> regardless of other patches. There is no point to keep it pending...
> All other changes, e.g. DTS will have to wait for more cycles till
> this gets in.
> 
> Therefore either please apply this or please comment what is stopping
> dependencies from being applied.

Indeed the first 3 (clk) patches should not be part of the series any more,
I have applied them few days ago - https://lkml.org/lkml/2019/6/6/554
Krzysztof Kozlowski June 14, 2019, 12:39 p.m. UTC | #3
On Fri, 14 Jun 2019 at 14:38, Sylwester Nawrocki <s.nawrocki@samsung.com> wrote:
>
> On 6/14/19 14:04, Krzysztof Kozlowski wrote:
> > I do not quite understand why this patch is still being resent instead
> > of have been applied some time ago. Are there any issues here? Or are
> > there any issues with the entire patchset (except some review comments
> > to be resolved)? If not, then this is a dependency which should go
> > regardless of other patches. There is no point to keep it pending...
> > All other changes, e.g. DTS will have to wait for more cycles till
> > this gets in.
> >
> > Therefore either please apply this or please comment what is stopping
> > dependencies from being applied.
>
> Indeed the first 3 (clk) patches should not be part of the series any more,
> I have applied them few days ago - https://lkml.org/lkml/2019/6/6/554

Ahhh, I missed that. Sorry for the noise then and thanks!

Best regards,
Krzysztof
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 355f469943f1..02d5ac469a3d 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -60,6 +60,7 @@ 
 #define CLK_MAU_EPLL		159
 #define CLK_SCLK_HSIC_12M	160
 #define CLK_SCLK_MPHY_IXTAL24	161
+#define CLK_SCLK_BPLL		162
 
 /* gate clocks */
 #define CLK_UART0		257
@@ -195,6 +196,16 @@ 
 #define CLK_ACLK432_CAM		518
 #define CLK_ACLK_FL1550_CAM	519
 #define CLK_ACLK550_CAM		520
+#define CLK_CLKM_PHY0		521
+#define CLK_CLKM_PHY1		522
+#define CLK_ACLK_PPMU_DREX0_0	523
+#define CLK_ACLK_PPMU_DREX0_1	524
+#define CLK_ACLK_PPMU_DREX1_0	525
+#define CLK_ACLK_PPMU_DREX1_1	526
+#define CLK_PCLK_PPMU_DREX0_0	527
+#define CLK_PCLK_PPMU_DREX0_1	528
+#define CLK_PCLK_PPMU_DREX1_0	529
+#define CLK_PCLK_PPMU_DREX1_1	530
 
 /* mux clocks */
 #define CLK_MOUT_HDMI		640
@@ -217,6 +228,8 @@ 
 #define CLK_MOUT_EPLL		657
 #define CLK_MOUT_MAU_EPLL	658
 #define CLK_MOUT_USER_MAU_EPLL	659
+#define CLK_MOUT_SCLK_SPLL	660
+#define CLK_MOUT_MX_MSPLL_CCORE_PHY	661
 
 /* divider clocks */
 #define CLK_DOUT_PIXEL		768
@@ -248,8 +261,11 @@ 
 #define CLK_DOUT_CCLK_DREX0	794
 #define CLK_DOUT_CLK2X_PHY0	795
 #define CLK_DOUT_PCLK_CORE_MEM	796
+#define CLK_FF_DOUT_SPLL2	797
+#define CLK_DOUT_PCLK_DREX0	798
+#define CLK_DOUT_PCLK_DREX1	799
 
 /* must be greater than maximal clock id */
-#define CLK_NR_CLKS		797
+#define CLK_NR_CLKS		800
 
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */