diff mbox

[rdma-core,03/17] Update comment in cxbg* drivers

Message ID 1475787103-13283-4-git-send-email-jgunthorpe@obsidianresearch.com (mailing list archive)
State Accepted
Headers show

Commit Message

Jason Gunthorpe Oct. 6, 2016, 8:51 p.m. UTC
The swap is correct on most arches we support, the note should be
to move this stuff to common code.

Fixes: 1df0888f6a73 ("Remove most checks of __BYTE_ORDER")
Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
---
 libcxgb3/src/cxio_wr.h | 3 +--
 libcxgb4/src/t4.h      | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

Comments

Steve Wise Oct. 6, 2016, 9:31 p.m. UTC | #1
> 
> The swap is correct on most arches we support, the note should be
> to move this stuff to common code.
> 
> Fixes: 1df0888f6a73 ("Remove most checks of __BYTE_ORDER")
> Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>

This looks good.

Reviewed-by: Steve Wise <swise@opengridcomputing.com>


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diff mbox

Patch

diff --git a/libcxgb3/src/cxio_wr.h b/libcxgb3/src/cxio_wr.h
index e24c7fed7d76..e15479540598 100644
--- a/libcxgb3/src/cxio_wr.h
+++ b/libcxgb3/src/cxio_wr.h
@@ -50,8 +50,7 @@ 
 #define Q_COUNT(rptr,wptr) ((wptr)-(rptr))
 #define Q_PTR2IDX(ptr,size_log2) (ptr & ((1UL<<size_log2)-1))
 
-/* Generally speaking, PCI systems auto-byteswap on PCI accesses, so this is
-   probably wrong */
+/* FIXME: Move me to a generic PCI mmio accessor */
 #define cpu_to_pci32(val) htole32(val)
 
 #define RING_DOORBELL(doorbell, QPID) { \
diff --git a/libcxgb4/src/t4.h b/libcxgb4/src/t4.h
index 45de5e3a7f71..eda9a203295d 100644
--- a/libcxgb4/src/t4.h
+++ b/libcxgb4/src/t4.h
@@ -63,8 +63,7 @@ 
 #define ROUND_UP(x, n) (((x) + (n) - 1u) & ~((n) - 1u))
 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
 
-/* Generally speaking, PCI systems auto-byteswap on PCI accesses, so this is
-   probably wrong */
+/* FIXME: Move me to a generic PCI mmio accessor */
 #define cpu_to_pci32(val) htole32(val)
 
 #define writel(v, a) do { *((volatile u32 *)(a)) = cpu_to_pci32(v); } while (0)