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[for-next,08/11] {topost} RDMA/hns: Add sq_invld_flg field in QP context

Message ID 1510304153-91394-9-git-send-email-oulijun@huawei.com (mailing list archive)
State Accepted
Headers show

Commit Message

Lijun Ou Nov. 10, 2017, 8:55 a.m. UTC 
In hip08 RoCE, it need to add the sq_invld_flg field
in QP context for RoCE hardware.

Signed-off-by: Lijun Ou <oulijun@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
Signed-off-by: Shaobo Xu <xushaobo2@huawei.com>
Signed-off-by: Yixian Liu <liuyixian@huawei.com>
---
 drivers/infiniband/hw/hns/hns_roce_hw_v2.c | 2 ++
 drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 6 ++++--
 2 files changed, 6 insertions(+), 2 deletions(-)
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Patch

diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
index d74a522..c1f3325 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@ -2042,6 +2042,8 @@  static void modify_qp_reset_to_init(struct ib_qp *ibqp,
 
 	roce_set_bit(qpc_mask->byte_168_irrl_idx,
 		     V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S, 0);
+	roce_set_bit(qpc_mask->byte_168_irrl_idx,
+		     V2_QPC_BYTE_168_SQ_INVLD_FLG_S, 0);
 	roce_set_field(qpc_mask->byte_168_irrl_idx,
 		       V2_QPC_BYTE_168_IRRL_IDX_LSB_M,
 		       V2_QPC_BYTE_168_IRRL_IDX_LSB_S, 0);
diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
index 3d9114e..04b7a51 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
@@ -606,8 +606,10 @@  struct hns_roce_v2_qp_context {
 
 #define V2_QPC_BYTE_168_MSG_RTY_LP_FLG_S 20
 
-#define	V2_QPC_BYTE_168_LP_SGEN_INI_S 21
-#define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 21)
+#define V2_QPC_BYTE_168_SQ_INVLD_FLG_S 21
+
+#define	V2_QPC_BYTE_168_LP_SGEN_INI_S 22
+#define V2_QPC_BYTE_168_LP_SGEN_INI_M GENMASK(23, 22)
 
 #define	V2_QPC_BYTE_168_SQ_SHIFT_BAK_S 24
 #define V2_QPC_BYTE_168_SQ_SHIFT_BAK_M GENMASK(27, 24)