[V3,for-next,1/5] RDMA/hns: Eliminate the warnings by sparse checking

Message ID	1530860537-42235-2-git-send-email-oulijun@huawei.com (mailing list archive)
State	Superseded
Headers	show Return-Path: <linux-rdma-owner@kernel.org> From: Lijun Ou <oulijun@huawei.com> To: <dledford@redhat.com>, <jgg@mellanox.com> CC: <leon@kernel.org>, <linux-rdma@vger.kernel.org> Subject: [PATCH V3 for-next 1/5] RDMA/hns: Eliminate the warnings by sparse checking Date: Fri, 6 Jul 2018 15:02:13 +0800 Message-ID: <1530860537-42235-2-git-send-email-oulijun@huawei.com> In-Reply-To: <1530860537-42235-1-git-send-email-oulijun@huawei.com> References: <1530860537-42235-1-git-send-email-oulijun@huawei.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-rdma-owner@vger.kernel.org Precedence: bulk

Hi Lijun, I love your patch! Perhaps something to improve: [auto build test WARNING on rdma/for-next] [also build test WARNING on v4.18-rc3 next-20180706] [cannot apply to linus/master linux-sof-driver/master] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Lijun-Ou/Four-cmd-queues-support-and-sparse-checking/20180706-143224 base: https://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git for-next reproduce: # apt-get install sparse make ARCH=x86_64 allmodconfig make C=1 CF=-D__CHECK_ENDIAN__ sparse warnings: (new ones prefixed by >>) drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1222:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1222:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1230:9: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1230:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1230:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1230:9: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1230:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1230:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1238:9: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1238:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1238:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1238:9: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1238:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1238:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1242:9: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1242:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1242:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1242:9: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1242:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1242:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1243:9: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1243:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1243:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1243:9: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1243:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1243:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1247:9: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1247:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1247:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1247:9: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1247:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1247:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1254:9: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1254:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1254:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1254:9: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1254:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1254:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1286:17: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1286:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1286:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1286:17: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1286:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1286:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1293:17: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1293:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1293:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1293:17: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1293:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1293:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1524:29: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1525:34: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1527:34: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1529:39: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:1583:36: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2452:17: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2452:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2452:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2452:17: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2452:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2452:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2457:17: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2457:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2457:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2457:17: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2457:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2457:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2462:17: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2462:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2462:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2462:17: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2462:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2462:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2472:9: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2472:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2472:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2472:9: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2472:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2472:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2474:9: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2474:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2474:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2474:9: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2474:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2474:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2475:9: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2475:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2475:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2475:9: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2475:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2475:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2497:9: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2497:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2497:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2497:9: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2497:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2497:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2499:28: sparse: incorrect type in argument 1 (different base types) @@ expected restricted __le32 [usertype] *val @@ got 2 [usertype] *val @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2499:28: expected restricted __le32 [usertype] *val drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2499:28: got unsigned int *<noident> >> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2626:37: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] sq_rq_bt_l @@ got unsignrestricted __le32 [usertype] sq_rq_bt_l @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2626:37: expected restricted __le32 [usertype] sq_rq_bt_l drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2626:37: got unsigned int [unsigned] [usertype] <noident> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2636:17: sparse: cast from restricted __le32 >> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2652:42: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] cur_rq_wqe_ba_l @@ got unsignrestricted __le32 [usertype] cur_rq_wqe_ba_l @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2652:42: expected restricted __le32 [usertype] cur_rq_wqe_ba_l drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2652:42: got unsigned int [unsigned] [usertype] <noident> >> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2671:43: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] cur_sq_wqe_ba_l @@ got unsignrestricted __le32 [usertype] cur_sq_wqe_ba_l @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2671:43: expected restricted __le32 [usertype] cur_sq_wqe_ba_l drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2671:43: got unsigned int [unsigned] [usertype] <noident> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2686:31: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [unsigned] val @@ got restrunsigned int [unsigned] val @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2686:31: expected unsigned int [unsigned] val drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2686:31: got restricted __le32 [usertype] qp1c_bytes_4 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2687:31: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [unsigned] val @@ got restrunsigned int [unsigned] val @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2687:31: expected unsigned int [unsigned] val drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2687:31: got restricted __le32 [usertype] sq_rq_bt_l drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2688:31: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [unsigned] val @@ got restrunsigned int [unsigned] val @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2688:31: expected unsigned int [unsigned] val drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2688:31: got restricted __le32 [usertype] qp1c_bytes_12 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2689:31: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [unsigned] val @@ got restrunsigned int [unsigned] val @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2689:31: expected unsigned int [unsigned] val drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2689:31: got restricted __le32 [usertype] qp1c_bytes_16 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2690:31: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [unsigned] val @@ got restrunsigned int [unsigned] val @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2690:31: expected unsigned int [unsigned] val drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2690:31: got restricted __le32 [usertype] qp1c_bytes_20 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2691:31: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [unsigned] val @@ got restrunsigned int [unsigned] val @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2691:31: expected unsigned int [unsigned] val drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2691:31: got restricted __le32 [usertype] cur_rq_wqe_ba_l drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2692:31: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [unsigned] val @@ got restrunsigned int [unsigned] val @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2692:31: expected unsigned int [unsigned] val drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2692:31: got restricted __le32 [usertype] qp1c_bytes_28 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2693:31: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [unsigned] val @@ got restrunsigned int [unsigned] val @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2693:31: expected unsigned int [unsigned] val drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2693:31: got restricted __le32 [usertype] qp1c_bytes_32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2694:31: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [unsigned] val @@ got restrunsigned int [unsigned] val @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2694:31: expected unsigned int [unsigned] val drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2694:31: got restricted __le32 [usertype] cur_sq_wqe_ba_l drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2695:31: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [unsigned] val @@ got restrunsigned int [unsigned] val @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2695:31: expected unsigned int [unsigned] val drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2695:31: got restricted __le32 [usertype] qp1c_bytes_40 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2701:9: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2701:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2701:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2701:9: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2701:9: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2701:9: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2915:37: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] sq_rq_bt_l @@ got unsignrestricted __le32 [usertype] sq_rq_bt_l @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2915:37: expected restricted __le32 [usertype] sq_rq_bt_l drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2915:37: got unsigned int [unsigned] [usertype] <noident> >> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2927:36: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] irrl_ba_l @@ got unsignrestricted __le32 [usertype] irrl_ba_l @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2927:36: expected restricted __le32 [usertype] irrl_ba_l drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2927:36: got unsigned int [unsigned] [usertype] <noident> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:2939:17: sparse: cast from restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3019:42: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] cur_rq_wqe_ba_l @@ got unsignrestricted __le32 [usertype] cur_rq_wqe_ba_l @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3019:42: expected restricted __le32 [usertype] cur_rq_wqe_ba_l drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3019:42: got unsigned int [unsigned] [usertype] <noident> >> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3099:45: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] rx_cur_sq_wqe_ba_l @@ got unsignrestricted __le32 [usertype] rx_cur_sq_wqe_ba_l @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3099:45: expected restricted __le32 [usertype] rx_cur_sq_wqe_ba_l drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3099:45: got unsigned int [unsigned] [usertype] <noident> >> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3247:45: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] tx_cur_sq_wqe_ba_l @@ got unsignrestricted __le32 [usertype] tx_cur_sq_wqe_ba_l @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3247:45: expected restricted __le32 [usertype] tx_cur_sq_wqe_ba_l drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3247:45: got unsigned int [unsigned] [usertype] <noident> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3294:17: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3294:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3294:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3294:17: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3294:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3294:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3296:17: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3296:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3296:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3296:17: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3296:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3296:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3298:17: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3298:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3298:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3298:17: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3298:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3298:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3300:17: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3300:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3300:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3300:17: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3300:17: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3300:17: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3308:36: sparse: incorrect type in argument 1 (different base types) @@ expected restricted __le32 [usertype] *val @@ got 2 [usertype] *val @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3308:36: expected restricted __le32 [usertype] *val drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3308:36: got unsigned int *<noident> >> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3414:30: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] qp1c_bytes_4 @@ got [usertype] qp1c_bytes_4 @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3414:30: expected restricted __le32 [usertype] qp1c_bytes_4 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3414:30: got unsigned int >> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3415:28: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] sq_rq_bt_l @@ got [usertype] sq_rq_bt_l @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3415:28: expected restricted __le32 [usertype] sq_rq_bt_l drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3415:28: got unsigned int >> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3416:31: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] qp1c_bytes_12 @@ got [usertype] qp1c_bytes_12 @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3416:31: expected restricted __le32 [usertype] qp1c_bytes_12 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3416:31: got unsigned int >> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3417:31: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] qp1c_bytes_16 @@ got [usertype] qp1c_bytes_16 @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3417:31: expected restricted __le32 [usertype] qp1c_bytes_16 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3417:31: got unsigned int >> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3418:31: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] qp1c_bytes_20 @@ got [usertype] qp1c_bytes_20 @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3418:31: expected restricted __le32 [usertype] qp1c_bytes_20 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3418:31: got unsigned int >> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3419:33: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] cur_rq_wqe_ba_l @@ got [usertype] cur_rq_wqe_ba_l @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3419:33: expected restricted __le32 [usertype] cur_rq_wqe_ba_l drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3419:33: got unsigned int >> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3420:31: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] qp1c_bytes_28 @@ got [usertype] qp1c_bytes_28 @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3420:31: expected restricted __le32 [usertype] qp1c_bytes_28 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3420:31: got unsigned int >> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3421:31: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] qp1c_bytes_32 @@ got [usertype] qp1c_bytes_32 @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3421:31: expected restricted __le32 [usertype] qp1c_bytes_32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3421:31: got unsigned int >> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3422:33: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] cur_sq_wqe_ba_l @@ got [usertype] cur_sq_wqe_ba_l @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3422:33: expected restricted __le32 [usertype] cur_sq_wqe_ba_l drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3422:33: got unsigned int >> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3423:31: sparse: incorrect type in assignment (different base types) @@ expected restricted __le32 [usertype] qp1c_bytes_40 @@ got [usertype] qp1c_bytes_40 @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3423:31: expected restricted __le32 [usertype] qp1c_bytes_40 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3423:31: got unsigned int >> drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3585:28: sparse: incorrect type in assignment (different base types) @@ expected unsigned char [unsigned] [usertype] rnr_retry @@ got d char [unsigned] [usertype] rnr_retry @@ drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3585:28: expected unsigned char [unsigned] [usertype] rnr_retry drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3585:28: got restricted __le32 [usertype] rnr_retry drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3630:19: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3633:19: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3636:14: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3637:27: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3640:27: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3646:27: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3652:36: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3655:36: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3658:25: sparse: invalid assignment: &= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3658:25: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3658:25: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3658:25: sparse: invalid assignment: |= drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3658:25: left side has type unsigned int drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3658:25: right side has type restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3707:21: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3710:21: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:3718:37: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:4025:17: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:4060:17: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:4096:15: sparse: cast to restricted __le32 drivers/infiniband/hw/hns/hns_roce_hw_v1.c:4099:20: sparse: too many warnings include/linux/slab.h:631:13: sparse: undefined identifier '__builtin_mul_overflow' include/linux/slab.h:631:13: sparse: not a function <noident> include/linux/slab.h:631:13: sparse: not a function <noident> vim +2626 drivers/infiniband/hw/hns/hns_roce_hw_v1.c 9a443537 oulijun 2016-07-21 2436 d61d6de0 Bart Van Assche 2017-10-11 2437 static int hns_roce_v1_clear_hem(struct hns_roce_dev *hr_dev, d61d6de0 Bart Van Assche 2017-10-11 2438 struct hns_roce_hem_table *table, int obj, d61d6de0 Bart Van Assche 2017-10-11 2439 int step_idx) 97f0e39f Wei Hu (Xavier 2016-09-20 2440) { 97f0e39f Wei Hu (Xavier 2016-09-20 2441) struct device *dev = &hr_dev->pdev->dev; 97f0e39f Wei Hu (Xavier 2016-09-20 2442) struct hns_roce_v1_priv *priv; 97f0e39f Wei Hu (Xavier 2016-09-20 2443) unsigned long end = 0, flags = 0; 97f0e39f Wei Hu (Xavier 2016-09-20 2444) uint32_t bt_cmd_val[2] = {0}; 97f0e39f Wei Hu (Xavier 2016-09-20 2445) void __iomem *bt_cmd; 97f0e39f Wei Hu (Xavier 2016-09-20 2446) u64 bt_ba = 0; 97f0e39f Wei Hu (Xavier 2016-09-20 2447) 016a0059 Wei Hu(Xavier 2017-08-30 2448) priv = (struct hns_roce_v1_priv *)hr_dev->priv; 97f0e39f Wei Hu (Xavier 2016-09-20 2449) 97f0e39f Wei Hu (Xavier 2016-09-20 2450) switch (table->type) { 97f0e39f Wei Hu (Xavier 2016-09-20 2451) case HEM_TYPE_QPC: 97f0e39f Wei Hu (Xavier 2016-09-20 2452) roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M, 97f0e39f Wei Hu (Xavier 2016-09-20 2453) ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_QPC); 97f0e39f Wei Hu (Xavier 2016-09-20 2454) bt_ba = priv->bt_table.qpc_buf.map >> 12; 97f0e39f Wei Hu (Xavier 2016-09-20 2455) break; 97f0e39f Wei Hu (Xavier 2016-09-20 2456) case HEM_TYPE_MTPT: 97f0e39f Wei Hu (Xavier 2016-09-20 2457) roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M, 97f0e39f Wei Hu (Xavier 2016-09-20 2458) ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_MTPT); 97f0e39f Wei Hu (Xavier 2016-09-20 2459) bt_ba = priv->bt_table.mtpt_buf.map >> 12; 97f0e39f Wei Hu (Xavier 2016-09-20 2460) break; 97f0e39f Wei Hu (Xavier 2016-09-20 2461) case HEM_TYPE_CQC: 97f0e39f Wei Hu (Xavier 2016-09-20 2462) roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_M, 97f0e39f Wei Hu (Xavier 2016-09-20 2463) ROCEE_BT_CMD_H_ROCEE_BT_CMD_MDF_S, HEM_TYPE_CQC); 97f0e39f Wei Hu (Xavier 2016-09-20 2464) bt_ba = priv->bt_table.cqc_buf.map >> 12; 97f0e39f Wei Hu (Xavier 2016-09-20 2465) break; 97f0e39f Wei Hu (Xavier 2016-09-20 2466) case HEM_TYPE_SRQC: 97f0e39f Wei Hu (Xavier 2016-09-20 2467) dev_dbg(dev, "HEM_TYPE_SRQC not support.\n"); 97f0e39f Wei Hu (Xavier 2016-09-20 2468) return -EINVAL; 97f0e39f Wei Hu (Xavier 2016-09-20 2469) default: 97f0e39f Wei Hu (Xavier 2016-09-20 2470) return 0; 97f0e39f Wei Hu (Xavier 2016-09-20 2471) } 97f0e39f Wei Hu (Xavier 2016-09-20 2472) roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_M, 97f0e39f Wei Hu (Xavier 2016-09-20 2473) ROCEE_BT_CMD_H_ROCEE_BT_CMD_IN_MDF_S, obj); 97f0e39f Wei Hu (Xavier 2016-09-20 2474) roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_S, 0); 97f0e39f Wei Hu (Xavier 2016-09-20 2475) roce_set_bit(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_HW_SYNS_S, 1); 97f0e39f Wei Hu (Xavier 2016-09-20 2476) 97f0e39f Wei Hu (Xavier 2016-09-20 2477) spin_lock_irqsave(&hr_dev->bt_cmd_lock, flags); 97f0e39f Wei Hu (Xavier 2016-09-20 2478) 97f0e39f Wei Hu (Xavier 2016-09-20 2479) bt_cmd = hr_dev->reg_base + ROCEE_BT_CMD_H_REG; 97f0e39f Wei Hu (Xavier 2016-09-20 2480) 97f0e39f Wei Hu (Xavier 2016-09-20 2481) end = msecs_to_jiffies(HW_SYNC_TIMEOUT_MSECS) + jiffies; 97f0e39f Wei Hu (Xavier 2016-09-20 2482) while (1) { 97f0e39f Wei Hu (Xavier 2016-09-20 2483) if (readl(bt_cmd) >> BT_CMD_SYNC_SHIFT) { 97f0e39f Wei Hu (Xavier 2016-09-20 2484) if (!(time_before(jiffies, end))) { 97f0e39f Wei Hu (Xavier 2016-09-20 2485) dev_err(dev, "Write bt_cmd err,hw_sync is not zero.\n"); 97f0e39f Wei Hu (Xavier 2016-09-20 2486) spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, 97f0e39f Wei Hu (Xavier 2016-09-20 2487) flags); 97f0e39f Wei Hu (Xavier 2016-09-20 2488) return -EBUSY; 97f0e39f Wei Hu (Xavier 2016-09-20 2489) } 97f0e39f Wei Hu (Xavier 2016-09-20 2490) } else { 97f0e39f Wei Hu (Xavier 2016-09-20 2491) break; 97f0e39f Wei Hu (Xavier 2016-09-20 2492) } 97f0e39f Wei Hu (Xavier 2016-09-20 2493) msleep(HW_SYNC_SLEEP_TIME_INTERVAL); 97f0e39f Wei Hu (Xavier 2016-09-20 2494) } 97f0e39f Wei Hu (Xavier 2016-09-20 2495) 97f0e39f Wei Hu (Xavier 2016-09-20 2496) bt_cmd_val[0] = (uint32_t)bt_ba; 97f0e39f Wei Hu (Xavier 2016-09-20 @2497) roce_set_field(bt_cmd_val[1], ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_M, 97f0e39f Wei Hu (Xavier 2016-09-20 2498) ROCEE_BT_CMD_H_ROCEE_BT_CMD_BA_H_S, bt_ba >> 32); 97f0e39f Wei Hu (Xavier 2016-09-20 @2499) hns_roce_write64_k(bt_cmd_val, hr_dev->reg_base + ROCEE_BT_CMD_L_REG); 97f0e39f Wei Hu (Xavier 2016-09-20 2500) 97f0e39f Wei Hu (Xavier 2016-09-20 2501) spin_unlock_irqrestore(&hr_dev->bt_cmd_lock, flags); 97f0e39f Wei Hu (Xavier 2016-09-20 2502) 97f0e39f Wei Hu (Xavier 2016-09-20 2503) return 0; 97f0e39f Wei Hu (Xavier 2016-09-20 2504) } 97f0e39f Wei Hu (Xavier 2016-09-20 2505) 9a443537 oulijun 2016-07-21 2506 static int hns_roce_v1_qp_modify(struct hns_roce_dev *hr_dev, 9a443537 oulijun 2016-07-21 2507 struct hns_roce_mtt *mtt, 9a443537 oulijun 2016-07-21 2508 enum hns_roce_qp_state cur_state, 9a443537 oulijun 2016-07-21 2509 enum hns_roce_qp_state new_state, 9a443537 oulijun 2016-07-21 2510 struct hns_roce_qp_context *context, 9a443537 oulijun 2016-07-21 2511 struct hns_roce_qp *hr_qp) 9a443537 oulijun 2016-07-21 2512 { 9a443537 oulijun 2016-07-21 2513 static const u16 9a443537 oulijun 2016-07-21 2514 op[HNS_ROCE_QP_NUM_STATE][HNS_ROCE_QP_NUM_STATE] = { 9a443537 oulijun 2016-07-21 2515 [HNS_ROCE_QP_STATE_RST] = { 9a443537 oulijun 2016-07-21 2516 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP, 9a443537 oulijun 2016-07-21 2517 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP, 9a443537 oulijun 2016-07-21 2518 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP, 9a443537 oulijun 2016-07-21 2519 }, 9a443537 oulijun 2016-07-21 2520 [HNS_ROCE_QP_STATE_INIT] = { 9a443537 oulijun 2016-07-21 2521 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP, 9a443537 oulijun 2016-07-21 2522 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP, 9a443537 oulijun 2016-07-21 2523 /* Note: In v1 engine, HW doesn't support RST2INIT. 9a443537 oulijun 2016-07-21 2524 * We use RST2INIT cmd instead of INIT2INIT. 9a443537 oulijun 2016-07-21 2525 */ 9a443537 oulijun 2016-07-21 2526 [HNS_ROCE_QP_STATE_INIT] = HNS_ROCE_CMD_RST2INIT_QP, 9a443537 oulijun 2016-07-21 2527 [HNS_ROCE_QP_STATE_RTR] = HNS_ROCE_CMD_INIT2RTR_QP, 9a443537 oulijun 2016-07-21 2528 }, 9a443537 oulijun 2016-07-21 2529 [HNS_ROCE_QP_STATE_RTR] = { 9a443537 oulijun 2016-07-21 2530 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP, 9a443537 oulijun 2016-07-21 2531 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP, 9a443537 oulijun 2016-07-21 2532 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTR2RTS_QP, 9a443537 oulijun 2016-07-21 2533 }, 9a443537 oulijun 2016-07-21 2534 [HNS_ROCE_QP_STATE_RTS] = { 9a443537 oulijun 2016-07-21 2535 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP, 9a443537 oulijun 2016-07-21 2536 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP, 9a443537 oulijun 2016-07-21 2537 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_RTS2RTS_QP, 9a443537 oulijun 2016-07-21 2538 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_RTS2SQD_QP, 9a443537 oulijun 2016-07-21 2539 }, 9a443537 oulijun 2016-07-21 2540 [HNS_ROCE_QP_STATE_SQD] = { 9a443537 oulijun 2016-07-21 2541 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP, 9a443537 oulijun 2016-07-21 2542 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP, 9a443537 oulijun 2016-07-21 2543 [HNS_ROCE_QP_STATE_RTS] = HNS_ROCE_CMD_SQD2RTS_QP, 9a443537 oulijun 2016-07-21 2544 [HNS_ROCE_QP_STATE_SQD] = HNS_ROCE_CMD_SQD2SQD_QP, 9a443537 oulijun 2016-07-21 2545 }, 9a443537 oulijun 2016-07-21 2546 [HNS_ROCE_QP_STATE_ERR] = { 9a443537 oulijun 2016-07-21 2547 [HNS_ROCE_QP_STATE_RST] = HNS_ROCE_CMD_2RST_QP, 9a443537 oulijun 2016-07-21 2548 [HNS_ROCE_QP_STATE_ERR] = HNS_ROCE_CMD_2ERR_QP, 9a443537 oulijun 2016-07-21 2549 } 9a443537 oulijun 2016-07-21 2550 }; 9a443537 oulijun 2016-07-21 2551 9a443537 oulijun 2016-07-21 2552 struct hns_roce_cmd_mailbox *mailbox; 9a443537 oulijun 2016-07-21 2553 struct device *dev = &hr_dev->pdev->dev; 9a443537 oulijun 2016-07-21 2554 int ret = 0; 9a443537 oulijun 2016-07-21 2555 9a443537 oulijun 2016-07-21 2556 if (cur_state >= HNS_ROCE_QP_NUM_STATE || 9a443537 oulijun 2016-07-21 2557 new_state >= HNS_ROCE_QP_NUM_STATE || 9a443537 oulijun 2016-07-21 2558 !op[cur_state][new_state]) { 9a443537 oulijun 2016-07-21 2559 dev_err(dev, "[modify_qp]not support state %d to %d\n", 9a443537 oulijun 2016-07-21 2560 cur_state, new_state); 9a443537 oulijun 2016-07-21 2561 return -EINVAL; 9a443537 oulijun 2016-07-21 2562 } 9a443537 oulijun 2016-07-21 2563 9a443537 oulijun 2016-07-21 2564 if (op[cur_state][new_state] == HNS_ROCE_CMD_2RST_QP) 9a443537 oulijun 2016-07-21 2565 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2, 9a443537 oulijun 2016-07-21 2566 HNS_ROCE_CMD_2RST_QP, 6b877c32 Wei Hu (Xavier 2016-11-23 2567) HNS_ROCE_CMD_TIMEOUT_MSECS); 9a443537 oulijun 2016-07-21 2568 9a443537 oulijun 2016-07-21 2569 if (op[cur_state][new_state] == HNS_ROCE_CMD_2ERR_QP) 9a443537 oulijun 2016-07-21 2570 return hns_roce_cmd_mbox(hr_dev, 0, 0, hr_qp->qpn, 2, 9a443537 oulijun 2016-07-21 2571 HNS_ROCE_CMD_2ERR_QP, 6b877c32 Wei Hu (Xavier 2016-11-23 2572) HNS_ROCE_CMD_TIMEOUT_MSECS); 9a443537 oulijun 2016-07-21 2573 9a443537 oulijun 2016-07-21 2574 mailbox = hns_roce_alloc_cmd_mailbox(hr_dev); 9a443537 oulijun 2016-07-21 2575 if (IS_ERR(mailbox)) 9a443537 oulijun 2016-07-21 2576 return PTR_ERR(mailbox); 9a443537 oulijun 2016-07-21 2577 9a443537 oulijun 2016-07-21 2578 memcpy(mailbox->buf, context, sizeof(*context)); 9a443537 oulijun 2016-07-21 2579 9a443537 oulijun 2016-07-21 2580 ret = hns_roce_cmd_mbox(hr_dev, mailbox->dma, 0, hr_qp->qpn, 0, 9a443537 oulijun 2016-07-21 2581 op[cur_state][new_state], 6b877c32 Wei Hu (Xavier 2016-11-23 2582) HNS_ROCE_CMD_TIMEOUT_MSECS); 9a443537 oulijun 2016-07-21 2583 9a443537 oulijun 2016-07-21 2584 hns_roce_free_cmd_mailbox(hr_dev, mailbox); 9a443537 oulijun 2016-07-21 2585 return ret; 9a443537 oulijun 2016-07-21 2586 } 9a443537 oulijun 2016-07-21 2587 9a443537 oulijun 2016-07-21 2588 static int hns_roce_v1_m_sqp(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 9a443537 oulijun 2016-07-21 2589 int attr_mask, enum ib_qp_state cur_state, 9a443537 oulijun 2016-07-21 2590 enum ib_qp_state new_state) 9a443537 oulijun 2016-07-21 2591 { 9a443537 oulijun 2016-07-21 2592 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device); 9a443537 oulijun 2016-07-21 2593 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp); 9a443537 oulijun 2016-07-21 2594 struct hns_roce_sqp_context *context; 9a443537 oulijun 2016-07-21 2595 struct device *dev = &hr_dev->pdev->dev; 9a443537 oulijun 2016-07-21 2596 dma_addr_t dma_handle = 0; 9a443537 oulijun 2016-07-21 2597 int rq_pa_start; 9a443537 oulijun 2016-07-21 2598 u32 reg_val; 9a443537 oulijun 2016-07-21 2599 u64 *mtts; cc4ed08b Bart Van Assche 2017-10-11 2600 u32 __iomem *addr; 9a443537 oulijun 2016-07-21 2601 9a443537 oulijun 2016-07-21 2602 context = kzalloc(sizeof(*context), GFP_KERNEL); 9a443537 oulijun 2016-07-21 2603 if (!context) 9a443537 oulijun 2016-07-21 2604 return -ENOMEM; 9a443537 oulijun 2016-07-21 2605 9a443537 oulijun 2016-07-21 2606 /* Search QP buf's MTTs */ 6a93c77a Shaobo Xu 2017-08-30 2607 mtts = hns_roce_table_find(hr_dev, &hr_dev->mr_table.mtt_table, 9a443537 oulijun 2016-07-21 2608 hr_qp->mtt.first_seg, &dma_handle); 9a443537 oulijun 2016-07-21 2609 if (!mtts) { 9a443537 oulijun 2016-07-21 2610 dev_err(dev, "qp buf pa find failed\n"); 9a443537 oulijun 2016-07-21 2611 goto out; 9a443537 oulijun 2016-07-21 2612 } 9a443537 oulijun 2016-07-21 2613 9a443537 oulijun 2016-07-21 2614 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) { 9a443537 oulijun 2016-07-21 2615 roce_set_field(context->qp1c_bytes_4, 9a443537 oulijun 2016-07-21 2616 QP1C_BYTES_4_SQ_WQE_SHIFT_M, 9a443537 oulijun 2016-07-21 2617 QP1C_BYTES_4_SQ_WQE_SHIFT_S, 9a443537 oulijun 2016-07-21 2618 ilog2((unsigned int)hr_qp->sq.wqe_cnt)); 9a443537 oulijun 2016-07-21 2619 roce_set_field(context->qp1c_bytes_4, 9a443537 oulijun 2016-07-21 2620 QP1C_BYTES_4_RQ_WQE_SHIFT_M, 9a443537 oulijun 2016-07-21 2621 QP1C_BYTES_4_RQ_WQE_SHIFT_S, 9a443537 oulijun 2016-07-21 2622 ilog2((unsigned int)hr_qp->rq.wqe_cnt)); 9a443537 oulijun 2016-07-21 2623 roce_set_field(context->qp1c_bytes_4, QP1C_BYTES_4_PD_M, 9a443537 oulijun 2016-07-21 2624 QP1C_BYTES_4_PD_S, to_hr_pd(ibqp->pd)->pdn); 9a443537 oulijun 2016-07-21 2625 9a443537 oulijun 2016-07-21 @2626 context->sq_rq_bt_l = (u32)(dma_handle); 9a443537 oulijun 2016-07-21 2627 roce_set_field(context->qp1c_bytes_12, 9a443537 oulijun 2016-07-21 2628 QP1C_BYTES_12_SQ_RQ_BT_H_M, 9a443537 oulijun 2016-07-21 2629 QP1C_BYTES_12_SQ_RQ_BT_H_S, 9a443537 oulijun 2016-07-21 2630 ((u32)(dma_handle >> 32))); 9a443537 oulijun 2016-07-21 2631 9a443537 oulijun 2016-07-21 2632 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_HEAD_M, 9a443537 oulijun 2016-07-21 2633 QP1C_BYTES_16_RQ_HEAD_S, hr_qp->rq.head); 9a443537 oulijun 2016-07-21 2634 roce_set_field(context->qp1c_bytes_16, QP1C_BYTES_16_PORT_NUM_M, 7716809e Lijun Ou 2016-09-15 2635 QP1C_BYTES_16_PORT_NUM_S, hr_qp->phy_port); 9a443537 oulijun 2016-07-21 2636 roce_set_bit(context->qp1c_bytes_16, 9a443537 oulijun 2016-07-21 2637 QP1C_BYTES_16_SIGNALING_TYPE_S, 9a443537 oulijun 2016-07-21 2638 hr_qp->sq_signal_bits); 9a443537 oulijun 2016-07-21 2639 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_RQ_BA_FLG_S, 9a443537 oulijun 2016-07-21 2640 1); 9a443537 oulijun 2016-07-21 2641 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_SQ_BA_FLG_S, 9a443537 oulijun 2016-07-21 2642 1); 9a443537 oulijun 2016-07-21 2643 roce_set_bit(context->qp1c_bytes_16, QP1C_BYTES_16_QP1_ERR_S, 9a443537 oulijun 2016-07-21 2644 0); 9a443537 oulijun 2016-07-21 2645 9a443537 oulijun 2016-07-21 2646 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_SQ_HEAD_M, 9a443537 oulijun 2016-07-21 2647 QP1C_BYTES_20_SQ_HEAD_S, hr_qp->sq.head); 9a443537 oulijun 2016-07-21 2648 roce_set_field(context->qp1c_bytes_20, QP1C_BYTES_20_PKEY_IDX_M, 9a443537 oulijun 2016-07-21 2649 QP1C_BYTES_20_PKEY_IDX_S, attr->pkey_index); 9a443537 oulijun 2016-07-21 2650 9a443537 oulijun 2016-07-21 2651 rq_pa_start = (u32)hr_qp->rq.offset / PAGE_SIZE; 9a443537 oulijun 2016-07-21 @2652 context->cur_rq_wqe_ba_l = (u32)(mtts[rq_pa_start]); 9a443537 oulijun 2016-07-21 2653 9a443537 oulijun 2016-07-21 2654 roce_set_field(context->qp1c_bytes_28, 9a443537 oulijun 2016-07-21 2655 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_M, 9a443537 oulijun 2016-07-21 2656 QP1C_BYTES_28_CUR_RQ_WQE_BA_H_S, 9a443537 oulijun 2016-07-21 2657 (mtts[rq_pa_start]) >> 32); 9a443537 oulijun 2016-07-21 2658 roce_set_field(context->qp1c_bytes_28, 9a443537 oulijun 2016-07-21 2659 QP1C_BYTES_28_RQ_CUR_IDX_M, 9a443537 oulijun 2016-07-21 2660 QP1C_BYTES_28_RQ_CUR_IDX_S, 0); 9a443537 oulijun 2016-07-21 2661 9a443537 oulijun 2016-07-21 2662 roce_set_field(context->qp1c_bytes_32, 9a443537 oulijun 2016-07-21 2663 QP1C_BYTES_32_RX_CQ_NUM_M, 9a443537 oulijun 2016-07-21 2664 QP1C_BYTES_32_RX_CQ_NUM_S, 9a443537 oulijun 2016-07-21 2665 to_hr_cq(ibqp->recv_cq)->cqn); 9a443537 oulijun 2016-07-21 2666 roce_set_field(context->qp1c_bytes_32, 9a443537 oulijun 2016-07-21 2667 QP1C_BYTES_32_TX_CQ_NUM_M, 9a443537 oulijun 2016-07-21 2668 QP1C_BYTES_32_TX_CQ_NUM_S, 9a443537 oulijun 2016-07-21 2669 to_hr_cq(ibqp->send_cq)->cqn); 9a443537 oulijun 2016-07-21 2670 9a443537 oulijun 2016-07-21 @2671 context->cur_sq_wqe_ba_l = (u32)mtts[0]; 9a443537 oulijun 2016-07-21 2672 9a443537 oulijun 2016-07-21 2673 roce_set_field(context->qp1c_bytes_40, 9a443537 oulijun 2016-07-21 2674 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_M, 9a443537 oulijun 2016-07-21 2675 QP1C_BYTES_40_CUR_SQ_WQE_BA_H_S, 9a443537 oulijun 2016-07-21 2676 (mtts[0]) >> 32); 9a443537 oulijun 2016-07-21 2677 roce_set_field(context->qp1c_bytes_40, 9a443537 oulijun 2016-07-21 2678 QP1C_BYTES_40_SQ_CUR_IDX_M, 9a443537 oulijun 2016-07-21 2679 QP1C_BYTES_40_SQ_CUR_IDX_S, 0); 9a443537 oulijun 2016-07-21 2680 9a443537 oulijun 2016-07-21 2681 /* Copy context to QP1C register */ cc4ed08b Bart Van Assche 2017-10-11 2682 addr = (u32 __iomem *)(hr_dev->reg_base + cc4ed08b Bart Van Assche 2017-10-11 2683 ROCEE_QP1C_CFG0_0_REG + 7716809e Lijun Ou 2016-09-15 2684 hr_qp->phy_port * sizeof(*context)); 9a443537 oulijun 2016-07-21 2685 9a443537 oulijun 2016-07-21 2686 writel(context->qp1c_bytes_4, addr); 9a443537 oulijun 2016-07-21 2687 writel(context->sq_rq_bt_l, addr + 1); 9a443537 oulijun 2016-07-21 2688 writel(context->qp1c_bytes_12, addr + 2); 9a443537 oulijun 2016-07-21 2689 writel(context->qp1c_bytes_16, addr + 3); 9a443537 oulijun 2016-07-21 2690 writel(context->qp1c_bytes_20, addr + 4); 9a443537 oulijun 2016-07-21 2691 writel(context->cur_rq_wqe_ba_l, addr + 5); 9a443537 oulijun 2016-07-21 2692 writel(context->qp1c_bytes_28, addr + 6); 9a443537 oulijun 2016-07-21 2693 writel(context->qp1c_bytes_32, addr + 7); 9a443537 oulijun 2016-07-21 2694 writel(context->cur_sq_wqe_ba_l, addr + 8); c24bf895 Lijun Ou 2016-09-15 2695 writel(context->qp1c_bytes_40, addr + 9); 9a443537 oulijun 2016-07-21 2696 } 9a443537 oulijun 2016-07-21 2697 9a443537 oulijun 2016-07-21 2698 /* Modify QP1C status */ 9a443537 oulijun 2016-07-21 2699 reg_val = roce_read(hr_dev, ROCEE_QP1C_CFG0_0_REG + 7716809e Lijun Ou 2016-09-15 2700 hr_qp->phy_port * sizeof(*context)); 9a443537 oulijun 2016-07-21 @2701 roce_set_field(reg_val, ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_M, 9a443537 oulijun 2016-07-21 2702 ROCEE_QP1C_CFG0_0_ROCEE_QP1C_QP_ST_S, new_state); 9a443537 oulijun 2016-07-21 2703 roce_write(hr_dev, ROCEE_QP1C_CFG0_0_REG + 7716809e Lijun Ou 2016-09-15 2704 hr_qp->phy_port * sizeof(*context), reg_val); 9a443537 oulijun 2016-07-21 2705 9a443537 oulijun 2016-07-21 2706 hr_qp->state = new_state; 9a443537 oulijun 2016-07-21 2707 if (new_state == IB_QPS_RESET) { 9a443537 oulijun 2016-07-21 2708 hns_roce_v1_cq_clean(to_hr_cq(ibqp->recv_cq), hr_qp->qpn, 9a443537 oulijun 2016-07-21 2709 ibqp->srq ? to_hr_srq(ibqp->srq) : NULL); 9a443537 oulijun 2016-07-21 2710 if (ibqp->send_cq != ibqp->recv_cq) 9a443537 oulijun 2016-07-21 2711 hns_roce_v1_cq_clean(to_hr_cq(ibqp->send_cq), 9a443537 oulijun 2016-07-21 2712 hr_qp->qpn, NULL); 9a443537 oulijun 2016-07-21 2713 9a443537 oulijun 2016-07-21 2714 hr_qp->rq.head = 0; 9a443537 oulijun 2016-07-21 2715 hr_qp->rq.tail = 0; 9a443537 oulijun 2016-07-21 2716 hr_qp->sq.head = 0; 9a443537 oulijun 2016-07-21 2717 hr_qp->sq.tail = 0; 9a443537 oulijun 2016-07-21 2718 hr_qp->sq_next_wqe = 0; 9a443537 oulijun 2016-07-21 2719 } 9a443537 oulijun 2016-07-21 2720 9a443537 oulijun 2016-07-21 2721 kfree(context); 9a443537 oulijun 2016-07-21 2722 return 0; 9a443537 oulijun 2016-07-21 2723 9a443537 oulijun 2016-07-21 2724 out: 9a443537 oulijun 2016-07-21 2725 kfree(context); 9a443537 oulijun 2016-07-21 2726 return -EINVAL; 9a443537 oulijun 2016-07-21 2727 } 9a443537 oulijun 2016-07-21 2728 :::::: The code at line 2626 was first introduced by commit :::::: 9a4435375cd151e07c0c38fa601b00115986091b IB/hns: Add driver files for hns RoCE driver :::::: TO: oulijun <oulijun@huawei.com> :::::: CC: Doug Ledford <dledford@redhat.com> --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation -- To unsubscribe from this list: send the line "unsubscribe linux-rdma" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html

diff --git a/drivers/infiniband/hw/hns/hns_roce_device.h b/drivers/infiniband/hw/hns/hns_roce_device.h index 65f7b68..c8101bd 100644 --- a/drivers/infiniband/hw/hns/hns_roce_device.h +++ b/drivers/infiniband/hw/hns/hns_roce_device.h @@ -864,7 +864,7 @@ static inline struct hns_roce_sqp *hr_to_hr_sqp(struct hns_roce_qp *hr_qp) return container_of(hr_qp, struct hns_roce_sqp, hr_qp); } -static inline void hns_roce_write64_k(__be32 val[2], void __iomem *dest) +static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) { __raw_writeq(*(u64 *) val, dest); } diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c index 235c67d..c8bc0be 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v1.c +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v1.c @@ -175,10 +175,10 @@ static int hns_roce_v1_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, UD_SEND_WQE_U32_36_FLOW_LABEL_M, UD_SEND_WQE_U32_36_FLOW_LABEL_S, 0); roce_set_field(ud_sq_wqe->u32_36, - UD_SEND_WQE_U32_36_PRIORITY_M, - UD_SEND_WQE_U32_36_PRIORITY_S, - ah->av.sl_tclass_flowlabel >> - HNS_ROCE_SL_SHIFT); + UD_SEND_WQE_U32_36_PRIORITY_M, + UD_SEND_WQE_U32_36_PRIORITY_S, + le32_to_cpu(ah->av.sl_tclass_flowlabel) >> + HNS_ROCE_SL_SHIFT); roce_set_field(ud_sq_wqe->u32_36, UD_SEND_WQE_U32_36_SGID_INDEX_M, UD_SEND_WQE_U32_36_SGID_INDEX_S, @@ -333,7 +333,7 @@ static int hns_roce_v1_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, doorbell[0] = le32_to_cpu(sq_db.u32_4); doorbell[1] = le32_to_cpu(sq_db.u32_8); - hns_roce_write64_k(doorbell, qp->sq.db_reg_l); + hns_roce_write64_k((__le32 *)doorbell, qp->sq.db_reg_l); qp->sq_next_wqe = ind; } @@ -349,7 +349,7 @@ static int hns_roce_v1_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, int nreq = 0; int ind = 0; int i = 0; - u32 reg_val = 0; + u32 reg_val; unsigned long flags = 0; struct hns_roce_rq_wqe_ctrl *ctrl = NULL; struct hns_roce_wqe_data_seg *scat = NULL; @@ -402,14 +402,18 @@ static int hns_roce_v1_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, wmb(); if (ibqp->qp_type == IB_QPT_GSI) { + __le32 tmp; + /* SW update GSI rq header */ reg_val = roce_read(to_hr_dev(ibqp->device), ROCEE_QP1C_CFG3_0_REG + QP1C_CFGN_OFFSET * hr_qp->phy_port); - roce_set_field(reg_val, + tmp = cpu_to_le32(reg_val); + roce_set_field(tmp, ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_M, ROCEE_QP1C_CFG3_0_ROCEE_QP1C_RQ_HEAD_S, hr_qp->rq.head); + reg_val = le32_to_cpu(tmp); roce_write(to_hr_dev(ibqp->device), ROCEE_QP1C_CFG3_0_REG + QP1C_CFGN_OFFSET * hr_qp->phy_port, reg_val); @@ -430,7 +434,8 @@ static int hns_roce_v1_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, doorbell[0] = le32_to_cpu(rq_db.u32_4); doorbell[1] = le32_to_cpu(rq_db.u32_8); - hns_roce_write64_k(doorbell, hr_qp->rq.db_reg_l); + hns_roce_write64_k((__le32 *)doorbell, + hr_qp->rq.db_reg_l); } } spin_unlock_irqrestore(&hr_qp->rq.lock, flags); @@ -441,51 +446,63 @@ static int hns_roce_v1_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr, static void hns_roce_set_db_event_mode(struct hns_roce_dev *hr_dev, int sdb_mode, int odb_mode) { + __le32 tmp; u32 val; val = roce_read(hr_dev, ROCEE_GLB_CFG_REG); - roce_set_bit(val, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode); - roce_set_bit(val, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode); + tmp = cpu_to_le32(val); + roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_SQ_MODE_S, sdb_mode); + roce_set_bit(tmp, ROCEE_GLB_CFG_ROCEE_DB_OTH_MODE_S, odb_mode); + val = le32_to_cpu(tmp); roce_write(hr_dev, ROCEE_GLB_CFG_REG, val); } static void hns_roce_set_db_ext_mode(struct hns_roce_dev *hr_dev, u32 sdb_mode, u32 odb_mode) { + __le32 tmp; u32 val; /* Configure SDB/ODB extend mode */ val = roce_read(hr_dev, ROCEE_GLB_CFG_REG); - roce_set_bit(val, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode); - roce_set_bit(val, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode); + tmp = cpu_to_le32(val); + roce_set_bit(tmp, ROCEE_GLB_CFG_SQ_EXT_DB_MODE_S, sdb_mode); + roce_set_bit(tmp, ROCEE_GLB_CFG_OTH_EXT_DB_MODE_S, odb_mode); + val = le32_to_cpu(tmp); roce_write(hr_dev, ROCEE_GLB_CFG_REG, val); } static void hns_roce_set_sdb(struct hns_roce_dev *hr_dev, u32 sdb_alept, u32 sdb_alful) { + __le32 tmp; u32 val; /* Configure SDB */ val = roce_read(hr_dev, ROCEE_DB_SQ_WL_REG); - roce_set_field(val, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M, + tmp = cpu_to_le32(val); + roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_M, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_S, sdb_alful); - roce_set_field(val, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M, + roce_set_field(tmp, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_M, ROCEE_DB_SQ_WL_ROCEE_DB_SQ_WL_EMPTY_S, sdb_alept); + val = le32_to_cpu(tmp); roce_write(hr_dev, ROCEE_DB_SQ_WL_REG, val); } static void hns_roce_set_odb(struct hns_roce_dev *hr_dev, u32 odb_alept, u32 odb_alful) { + __le32 tmp; u32 val; /* Configure ODB */ val = roce_read(hr_dev, ROCEE_DB_OTHERS_WL_REG); - roce_set_field(val, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M, + tmp = cpu_to_le32(val); + roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_M, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_S, odb_alful); - roce_set_field(val, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M, + roce_set_field(tmp, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_M, ROCEE_DB_OTHERS_WL_ROCEE_DB_OTH_WL_EMPTY_S, odb_alept); + val = le32_to_cpu(tmp); roce_write(hr_dev, ROCEE_DB_OTHERS_WL_REG, val); } @@ -496,6 +513,7 @@ static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept, struct hns_roce_v1_priv *priv; struct hns_roce_db_table *db; dma_addr_t sdb_dma_addr; + __le32 tmp; u32 val; priv = (struct hns_roce_v1_priv *)hr_dev->priv; @@ -511,7 +529,8 @@ static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept, /* Configure extend SDB depth */ val = roce_read(hr_dev, ROCEE_EXT_DB_SQ_H_REG); - roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M, + tmp = cpu_to_le32(val); + roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_M, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_SHIFT_S, db->ext_db->esdb_dep); /* @@ -519,8 +538,9 @@ static void hns_roce_set_sdb_ext(struct hns_roce_dev *hr_dev, u32 ext_sdb_alept, * using 4K page, and shift more 32 because of * caculating the high 32 bit value evaluated to hardware. */ - roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M, + roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_M, ROCEE_EXT_DB_SQ_H_EXT_DB_SQ_BA_H_S, sdb_dma_addr >> 44); + val = le32_to_cpu(tmp); roce_write(hr_dev, ROCEE_EXT_DB_SQ_H_REG, val); dev_dbg(dev, "ext SDB depth: 0x%x\n", db->ext_db->esdb_dep); @@ -535,6 +555,7 @@ static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept, struct hns_roce_v1_priv *priv; struct hns_roce_db_table *db; dma_addr_t odb_dma_addr; + __le32 tmp; u32 val; priv = (struct hns_roce_v1_priv *)hr_dev->priv; @@ -550,12 +571,14 @@ static void hns_roce_set_odb_ext(struct hns_roce_dev *hr_dev, u32 ext_odb_alept, /* Configure extend ODB depth */ val = roce_read(hr_dev, ROCEE_EXT_DB_OTH_H_REG); - roce_set_field(val, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M, + tmp = cpu_to_le32(val); + roce_set_field(tmp, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_M, ROCEE_EXT_DB_OTH_H_EXT_DB_OTH_SHIFT_S, db->ext_db->eodb_dep); - roce_set_field(val, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M, + roce_set_field(tmp, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_M, ROCEE_EXT_DB_SQ_H_EXT_DB_OTH_BA_H_S, db->ext_db->eodb_dep); + val = le32_to_cpu(tmp); roce_write(hr_dev, ROCEE_EXT_DB_OTH_H_REG, val); dev_dbg(dev, "ext ODB depth: 0x%x\n", db->ext_db->eodb_dep); @@ -1568,21 +1591,25 @@ static int hns_roce_v1_init(struct hns_roce_dev *hr_dev) { int ret; u32 val; + __le32 tmp; struct device *dev = &hr_dev->pdev->dev; /* DMAE user config */ val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG1_REG); - roce_set_field(val, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M, + tmp = cpu_to_le32(val); + roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_M, ROCEE_DMAE_USER_CFG1_ROCEE_CACHE_TB_CFG_S, 0xf); - roce_set_field(val, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M, + roce_set_field(tmp, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_M, ROCEE_DMAE_USER_CFG1_ROCEE_STREAM_ID_TB_CFG_S, 1 << PAGES_SHIFT_16); + val = le32_to_cpu(tmp); roce_write(hr_dev, ROCEE_DMAE_USER_CFG1_REG, val); val = roce_read(hr_dev, ROCEE_DMAE_USER_CFG2_REG); - roce_set_field(val, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M, + tmp = cpu_to_le32(val); + roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_M, ROCEE_DMAE_USER_CFG2_ROCEE_CACHE_PKT_CFG_S, 0xf); - roce_set_field(val, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M, + roce_set_field(tmp, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_M, ROCEE_DMAE_USER_CFG2_ROCEE_STREAM_ID_PKT_CFG_S, 1 << PAGES_SHIFT_16); @@ -1668,6 +1695,7 @@ static int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param, u32 __iomem *hcr = (u32 __iomem *)(hr_dev->reg_base + ROCEE_MB1_REG); unsigned long end; u32 val = 0; + __le32 tmp; end = msecs_to_jiffies(GO_BIT_TIMEOUT_MSECS) + jiffies; while (hns_roce_v1_cmd_pending(hr_dev)) { @@ -1679,15 +1707,17 @@ static int hns_roce_v1_post_mbox(struct hns_roce_dev *hr_dev, u64 in_param, cond_resched(); } - roce_set_field(val, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S, + tmp = cpu_to_le32(val); + roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_M, ROCEE_MB6_ROCEE_MB_CMD_S, op); - roce_set_field(val, ROCEE_MB6_ROCEE_MB_CMD_MDF_M, + roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_CMD_MDF_M, ROCEE_MB6_ROCEE_MB_CMD_MDF_S, op_modifier); - roce_set_bit(val, ROCEE_MB6_ROCEE_MB_EVENT_S, event); - roce_set_bit(val, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1); - roce_set_field(val, ROCEE_MB6_ROCEE_MB_TOKEN_M, + roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_EVENT_S, event); + roce_set_bit(tmp, ROCEE_MB6_ROCEE_MB_HW_RUN_S, 1); + roce_set_field(tmp, ROCEE_MB6_ROCEE_MB_TOKEN_M, ROCEE_MB6_ROCEE_MB_TOKEN_S, token); + val = le32_to_cpu(tmp); writeq(in_param, hcr + 0); writeq(out_param, hcr + 2); writel(in_modifier, hcr + 4); @@ -1717,7 +1747,7 @@ static int hns_roce_v1_chk_mbox(struct hns_roce_dev *hr_dev, return -ETIMEDOUT; } - status = le32_to_cpu((__force __be32) + status = le32_to_cpu((__force __le32) __raw_readl(hcr + HCR_STATUS_OFFSET)); if ((status & STATUS_MASK) != 0x1) { dev_err(hr_dev->dev, "mailbox status 0x%x!\n", status); @@ -1760,6 +1790,7 @@ static int hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, { u32 reg_smac_l; u16 reg_smac_h; + __le32 tmp; u16 *p_h; u32 *p; u32 val; @@ -1784,10 +1815,12 @@ static int hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, val = roce_read(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET); + tmp = cpu_to_le32(val); p_h = (u16 *)(&addr[4]); reg_smac_h = *p_h; - roce_set_field(val, ROCEE_SMAC_H_ROCEE_SMAC_H_M, + roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_SMAC_H_M, ROCEE_SMAC_H_ROCEE_SMAC_H_S, reg_smac_h); + val = le32_to_cpu(tmp); roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET, val); @@ -1797,12 +1830,15 @@ static int hns_roce_v1_set_mac(struct hns_roce_dev *hr_dev, u8 phy_port, static void hns_roce_v1_set_mtu(struct hns_roce_dev *hr_dev, u8 phy_port, enum ib_mtu mtu) { + __le32 tmp; u32 val; val = roce_read(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET); - roce_set_field(val, ROCEE_SMAC_H_ROCEE_PORT_MTU_M, + tmp = cpu_to_le32(val); + roce_set_field(tmp, ROCEE_SMAC_H_ROCEE_PORT_MTU_M, ROCEE_SMAC_H_ROCEE_PORT_MTU_S, mtu); + val = le32_to_cpu(tmp); roce_write(hr_dev, ROCEE_SMAC_H_0_REG + phy_port * PHY_PORT_OFFSET, val); } @@ -1848,9 +1884,9 @@ static int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr, roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_MW_BIND_COUNTER_M, MPT_BYTE_12_MW_BIND_COUNTER_S, 0); - mpt_entry->virt_addr_l = (u32)mr->iova; - mpt_entry->virt_addr_h = (u32)(mr->iova >> 32); - mpt_entry->length = (u32)mr->size; + mpt_entry->virt_addr_l = cpu_to_le32((u32)mr->iova); + mpt_entry->virt_addr_h = cpu_to_le32((u32)(mr->iova >> 32)); + mpt_entry->length = cpu_to_le32((u32)mr->size); roce_set_field(mpt_entry->mpt_byte_28, MPT_BYTE_28_PD_M, MPT_BYTE_28_PD_S, mr->pd); @@ -1885,64 +1921,59 @@ static int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr, roce_set_field(mpt_entry->mpt_byte_36, MPT_BYTE_36_PA0_H_M, MPT_BYTE_36_PA0_H_S, - cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_32))); + (u32)(pages[i] >> PAGES_SHIFT_32)); break; case 1: roce_set_field(mpt_entry->mpt_byte_36, MPT_BYTE_36_PA1_L_M, - MPT_BYTE_36_PA1_L_S, - cpu_to_le32((u32)(pages[i]))); + MPT_BYTE_36_PA1_L_S, (u32)(pages[i])); roce_set_field(mpt_entry->mpt_byte_40, MPT_BYTE_40_PA1_H_M, MPT_BYTE_40_PA1_H_S, - cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_24))); + (u32)(pages[i] >> PAGES_SHIFT_24)); break; case 2: roce_set_field(mpt_entry->mpt_byte_40, MPT_BYTE_40_PA2_L_M, - MPT_BYTE_40_PA2_L_S, - cpu_to_le32((u32)(pages[i]))); + MPT_BYTE_40_PA2_L_S, (u32)(pages[i])); roce_set_field(mpt_entry->mpt_byte_44, MPT_BYTE_44_PA2_H_M, MPT_BYTE_44_PA2_H_S, - cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_16))); + (u32)(pages[i] >> PAGES_SHIFT_16)); break; case 3: roce_set_field(mpt_entry->mpt_byte_44, MPT_BYTE_44_PA3_L_M, - MPT_BYTE_44_PA3_L_S, - cpu_to_le32((u32)(pages[i]))); + MPT_BYTE_44_PA3_L_S, (u32)(pages[i])); roce_set_field(mpt_entry->mpt_byte_48, MPT_BYTE_48_PA3_H_M, MPT_BYTE_48_PA3_H_S, - cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_8))); + (u32)(pages[i] >> PAGES_SHIFT_8)); break; case 4: mpt_entry->pa4_l = cpu_to_le32((u32)(pages[i])); roce_set_field(mpt_entry->mpt_byte_56, MPT_BYTE_56_PA4_H_M, MPT_BYTE_56_PA4_H_S, - cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_32))); + (u32)(pages[i] >> PAGES_SHIFT_32)); break; case 5: roce_set_field(mpt_entry->mpt_byte_56, MPT_BYTE_56_PA5_L_M, - MPT_BYTE_56_PA5_L_S, - cpu_to_le32((u32)(pages[i]))); + MPT_BYTE_56_PA5_L_S, (u32)(pages[i])); roce_set_field(mpt_entry->mpt_byte_60, MPT_BYTE_60_PA5_H_M, MPT_BYTE_60_PA5_H_S, - cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_24))); + (u32)(pages[i] >> PAGES_SHIFT_24)); break; case 6: roce_set_field(mpt_entry->mpt_byte_60, MPT_BYTE_60_PA6_L_M, - MPT_BYTE_60_PA6_L_S, - cpu_to_le32((u32)(pages[i]))); + MPT_BYTE_60_PA6_L_S, (u32)(pages[i])); roce_set_field(mpt_entry->mpt_byte_64, MPT_BYTE_64_PA6_H_M, MPT_BYTE_64_PA6_H_S, - cpu_to_le32((u32)(pages[i] >> PAGES_SHIFT_16))); + (u32)(pages[i] >> PAGES_SHIFT_16)); break; default: break; @@ -1951,7 +1982,7 @@ static int hns_roce_v1_write_mtpt(void *mb_buf, struct hns_roce_mr *mr, free_page((unsigned long) pages); - mpt_entry->pbl_addr_l = (u32)(mr->pbl_dma_addr); + mpt_entry->pbl_addr_l = cpu_to_le32((u32)(mr->pbl_dma_addr)); roce_set_field(mpt_entry->mpt_byte_12, MPT_BYTE_12_PBL_ADDR_H_M, MPT_BYTE_12_PBL_ADDR_H_S, @@ -1982,9 +2013,9 @@ static struct hns_roce_cqe *next_cqe_sw(struct hns_roce_cq *hr_cq) static void hns_roce_v1_cq_set_ci(struct hns_roce_cq *hr_cq, u32 cons_index) { - u32 doorbell[2]; + __le32 doorbell[2]; - doorbell[0] = cons_index & ((hr_cq->cq_depth << 1) - 1); + doorbell[0] = cpu_to_le32(cons_index & ((hr_cq->cq_depth << 1) - 1)); doorbell[1] = 0; roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1); roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M, @@ -2081,10 +2112,8 @@ static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev, CQ_CONTEXT_CQC_BYTE_4_CQC_STATE_S, CQ_STATE_VALID); roce_set_field(cq_context->cqc_byte_4, CQ_CONTEXT_CQC_BYTE_4_CQN_M, CQ_CONTEXT_CQC_BYTE_4_CQN_S, hr_cq->cqn); - cq_context->cqc_byte_4 = cpu_to_le32(cq_context->cqc_byte_4); - cq_context->cq_bt_l = (u32)dma_handle; - cq_context->cq_bt_l = cpu_to_le32(cq_context->cq_bt_l); + cq_context->cq_bt_l = cpu_to_le32((u32)dma_handle); roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CQ_BT_H_M, @@ -2096,15 +2125,12 @@ static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev, ilog2((unsigned int)nent)); roce_set_field(cq_context->cqc_byte_12, CQ_CONTEXT_CQC_BYTE_12_CEQN_M, CQ_CONTEXT_CQC_BYTE_12_CEQN_S, vector); - cq_context->cqc_byte_12 = cpu_to_le32(cq_context->cqc_byte_12); - cq_context->cur_cqe_ba0_l = (u32)(mtts[0]); - cq_context->cur_cqe_ba0_l = cpu_to_le32(cq_context->cur_cqe_ba0_l); + cq_context->cur_cqe_ba0_l = cpu_to_le32((u32)(mtts[0])); roce_set_field(cq_context->cqc_byte_20, CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_M, - CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S, - cpu_to_le32((mtts[0]) >> 32)); + CQ_CONTEXT_CQC_BYTE_20_CUR_CQE_BA0_H_S, (mtts[0]) >> 32); /* Dedicated hardware, directly set 0 */ roce_set_field(cq_context->cqc_byte_20, CQ_CONTEXT_CQC_BYTE_20_CQ_CUR_INDEX_M, @@ -2118,9 +2144,8 @@ static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev, CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_M, CQ_CONTEXT_CQC_BYTE_20_CQE_TPTR_ADDR_H_S, tptr_dma_addr >> 44); - cq_context->cqc_byte_20 = cpu_to_le32(cq_context->cqc_byte_20); - cq_context->cqe_tptr_addr_l = (u32)(tptr_dma_addr >> 12); + cq_context->cqe_tptr_addr_l = cpu_to_le32((u32)(tptr_dma_addr >> 12)); roce_set_field(cq_context->cqc_byte_32, CQ_CONTEXT_CQC_BYTE_32_CUR_CQE_BA1_H_M, @@ -2138,7 +2163,6 @@ static void hns_roce_v1_write_cqc(struct hns_roce_dev *hr_dev, roce_set_field(cq_context->cqc_byte_32, CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_M, CQ_CONTEXT_CQC_BYTE_32_CQ_CONS_IDX_S, 0); - cq_context->cqc_byte_32 = cpu_to_le32(cq_context->cqc_byte_32); } static int hns_roce_v1_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period) @@ -2151,7 +2175,7 @@ static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq, { struct hns_roce_cq *hr_cq = to_hr_cq(ibcq); u32 notification_flag; - u32 doorbell[2]; + __le32 doorbell[2]; notification_flag = (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ? CQ_DB_REQ_NOT : CQ_DB_REQ_NOT_SOL; @@ -2159,7 +2183,8 @@ static int hns_roce_v1_req_notify_cq(struct ib_cq *ibcq, * flags = 0; Notification Flag = 1, next * flags = 1; Notification Flag = 0, solocited */ - doorbell[0] = hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1); + doorbell[0] = + cpu_to_le32(hr_cq->cons_index & ((hr_cq->cq_depth << 1) - 1)); roce_set_bit(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_HW_SYNS_S, 1); roce_set_field(doorbell[1], ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_M, ROCEE_DB_OTHERS_H_ROCEE_DB_OTH_CMD_S, 3); diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v1.h b/drivers/infiniband/hw/hns/hns_roce_hw_v1.h index e9a2717..6644014 100644 --- a/drivers/infiniband/hw/hns/hns_roce_hw_v1.h +++ b/drivers/infiniband/hw/hns/hns_roce_hw_v1.h @@ -260,7 +260,7 @@ struct hns_roce_cqe { __le32 cqe_byte_4; union { __le32 r_key; - __be32 immediate_data; + __le32 immediate_data; }; __le32 byte_cnt; __le32 cqe_byte_16;

[V3,for-next,1/5] RDMA/hns: Eliminate the warnings by sparse checking

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