@@ -68,7 +68,7 @@ static int mana_ib_probe(struct auxiliary_device *adev,
ibdev_dbg(&mib_dev->ib_dev, "mdev=%p id=%d num_ports=%d\n", mdev,
mdev->dev_id.as_uint32, mib_dev->ib_dev.phys_port_cnt);
- mib_dev->gdma_dev = mdev;
+ mib_dev->gc = mdev->gdma_context;
mib_dev->ib_dev.node_type = RDMA_NODE_IB_CA;
/*
@@ -85,15 +85,23 @@ static int mana_ib_probe(struct auxiliary_device *adev,
goto free_ib_device;
}
+ ret = mana_ib_create_error_eq(mib_dev);
+ if (ret) {
+ ibdev_err(&mib_dev->ib_dev, "Failed to allocate err eq");
+ goto deregister_device;
+ }
+
ret = ib_register_device(&mib_dev->ib_dev, "mana_%d",
mdev->gdma_context->dev);
if (ret)
- goto deregister_device;
+ goto free_error_eq;
dev_set_drvdata(&adev->dev, mib_dev);
return 0;
+free_error_eq:
+ mana_gd_destroy_queue(mib_dev->gc, mib_dev->fatal_err_eq);
deregister_device:
mana_gd_deregister_device(&mib_dev->gc->mana_ib);
free_ib_device:
@@ -105,6 +113,7 @@ static void mana_ib_remove(struct auxiliary_device *adev)
{
struct mana_ib_dev *mib_dev = dev_get_drvdata(&adev->dev);
+ mana_gd_destroy_queue(mib_dev->gc, mib_dev->fatal_err_eq);
mana_gd_deregister_device(&mib_dev->gc->mana_ib);
ib_unregister_device(&mib_dev->ib_dev);
ib_dealloc_device(&mib_dev->ib_dev);
@@ -504,3 +504,47 @@ int mana_ib_query_gid(struct ib_device *ibdev, u32 port, int index,
void mana_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
{
}
+
+void mana_ib_soc_event_handler(void *ctx, struct gdma_queue *queue,
+ struct gdma_event *event)
+{
+ struct mana_ib_dev *mib_dev = (struct mana_ib_dev *)ctx;
+
+ switch (event->type) {
+ case GDMA_EQE_SOC_EVENT_NOTIFICATION:
+ ibdev_info(&mib_dev->ib_dev, "Received SOC Notification");
+ break;
+ case GDMA_EQE_SOC_EVENT_TEST:
+ ibdev_info(&mib_dev->ib_dev, "Received SoC Test");
+ break;
+ default:
+ ibdev_err(&mib_dev->ib_dev, "Received unsolicited evt %d",
+ event->type);
+ }
+}
+
+int mana_ib_create_error_eq(struct mana_ib_dev *mib_dev)
+{
+ struct gdma_queue_spec spec = {};
+ int err;
+
+ spec.type = GDMA_EQ;
+ spec.monitor_avl_buf = false;
+ spec.queue_size = EQ_SIZE;
+ spec.eq.callback = mana_ib_soc_event_handler;
+ spec.eq.context = mib_dev;
+ spec.eq.log2_throttle_limit = LOG2_EQ_THROTTLE;
+ spec.eq.msix_allocated = true;
+ spec.eq.msix_index = 0;
+ spec.doorbell = mib_dev->gc->mana_ib.doorbell;
+ spec.pdid = mib_dev->gc->mana_ib.pdid;
+
+ err = mana_gd_create_mana_eq(&mib_dev->gc->mana_ib, &spec,
+ &mib_dev->fatal_err_eq);
+ if (err)
+ return err;
+
+ mib_dev->fatal_err_eq->eq.disable_needed = true;
+
+ return 0;
+}
@@ -31,6 +31,7 @@ struct mana_ib_dev {
struct ib_device ib_dev;
struct gdma_dev *gdma_dev;
struct gdma_context *gc;
+ struct gdma_queue *fatal_err_eq;
};
struct mana_ib_wq {
@@ -161,4 +162,6 @@ int mana_ib_query_gid(struct ib_device *ibdev, u32 port, int index,
void mana_ib_disassociate_ucontext(struct ib_ucontext *ibcontext);
+int mana_ib_create_error_eq(struct mana_ib_dev *mib_dev);
+
#endif
@@ -185,7 +185,8 @@ void mana_gd_free_memory(struct gdma_mem_info *gmi)
}
static int mana_gd_create_hw_eq(struct gdma_context *gc,
- struct gdma_queue *queue)
+ struct gdma_queue *queue,
+ u32 doorbell, u32 pdid)
{
struct gdma_create_queue_resp resp = {};
struct gdma_create_queue_req req = {};
@@ -199,8 +200,8 @@ static int mana_gd_create_hw_eq(struct gdma_context *gc,
req.hdr.dev_id = queue->gdma_dev->dev_id;
req.type = queue->type;
- req.pdid = queue->gdma_dev->pdid;
- req.doolbell_id = queue->gdma_dev->doorbell;
+ req.pdid = pdid;
+ req.doolbell_id = doorbell;
req.gdma_region = queue->mem_info.dma_region_handle;
req.queue_size = queue->queue_size;
req.log2_throttle_limit = queue->eq.log2_throttle_limit;
@@ -371,53 +372,51 @@ static void mana_gd_process_eqe(struct gdma_queue *eq)
}
}
-static void mana_gd_process_eq_events(void *arg)
+static void mana_gd_process_eq_events(struct list_head *eq_list)
{
u32 owner_bits, new_bits, old_bits;
union gdma_eqe_info eqe_info;
struct gdma_eqe *eq_eqe_ptr;
- struct gdma_queue *eq = arg;
+ struct gdma_queue *eq;
struct gdma_context *gc;
struct gdma_eqe *eqe;
u32 head, num_eqe;
int i;
- gc = eq->gdma_dev->gdma_context;
-
- num_eqe = eq->queue_size / GDMA_EQE_SIZE;
- eq_eqe_ptr = eq->queue_mem_ptr;
-
- /* Process up to 5 EQEs at a time, and update the HW head. */
- for (i = 0; i < 5; i++) {
- eqe = &eq_eqe_ptr[eq->head % num_eqe];
- eqe_info.as_uint32 = eqe->eqe_info;
- owner_bits = eqe_info.owner_bits;
-
- old_bits = (eq->head / num_eqe - 1) & GDMA_EQE_OWNER_MASK;
- /* No more entries */
- if (owner_bits == old_bits)
- break;
-
- new_bits = (eq->head / num_eqe) & GDMA_EQE_OWNER_MASK;
- if (owner_bits != new_bits) {
- dev_err(gc->dev, "EQ %d: overflow detected\n", eq->id);
- break;
+ list_for_each_entry_rcu(eq, eq_list, entry) {
+ gc = eq->gdma_dev->gdma_context;
+
+ num_eqe = eq->queue_size / GDMA_EQE_SIZE;
+ eq_eqe_ptr = eq->queue_mem_ptr;
+ /* Process up to 5 EQEs at a time, and update the HW head. */
+ for (i = 0; i < 5; i++) {
+ eqe = &eq_eqe_ptr[eq->head % num_eqe];
+ eqe_info.as_uint32 = eqe->eqe_info;
+ owner_bits = eqe_info.owner_bits;
+
+ old_bits = (eq->head / num_eqe - 1) & GDMA_EQE_OWNER_MASK;
+ /* No more entries */
+ if (owner_bits == old_bits)
+ break;
+
+ new_bits = (eq->head / num_eqe) & GDMA_EQE_OWNER_MASK;
+ if (owner_bits != new_bits) {
+ dev_err(gc->dev, "EQ %d: overflow detected\n",
+ eq->id);
+ break;
+ }
+ /* Per GDMA spec, rmb is necessary after checking owner_bits, before
+ * reading eqe.
+ */
+ rmb();
+ mana_gd_process_eqe(eq);
+ eq->head++;
}
- /* Per GDMA spec, rmb is necessary after checking owner_bits, before
- * reading eqe.
- */
- rmb();
-
- mana_gd_process_eqe(eq);
-
- eq->head++;
+ head = eq->head % (num_eqe << GDMA_EQE_OWNER_BITS);
+ mana_gd_ring_doorbell(gc, eq->gdma_dev->doorbell, eq->type,
+ eq->id, head, SET_ARM_BIT);
}
-
- head = eq->head % (num_eqe << GDMA_EQE_OWNER_BITS);
-
- mana_gd_ring_doorbell(gc, eq->gdma_dev->doorbell, eq->type, eq->id,
- head, SET_ARM_BIT);
}
static int mana_gd_register_irq(struct gdma_queue *queue,
@@ -435,44 +434,47 @@ static int mana_gd_register_irq(struct gdma_queue *queue,
gc = gd->gdma_context;
r = &gc->msix_resource;
dev = gc->dev;
+ msi_index = spec->eq.msix_index;
spin_lock_irqsave(&r->lock, flags);
- msi_index = find_first_zero_bit(r->map, r->size);
- if (msi_index >= r->size || msi_index >= gc->num_msix_usable) {
- err = -ENOSPC;
- } else {
- bitmap_set(r->map, msi_index, 1);
- queue->eq.msix_index = msi_index;
- }
-
- spin_unlock_irqrestore(&r->lock, flags);
+ if (!spec->eq.msix_allocated) {
+ msi_index = find_first_zero_bit(r->map, r->size);
- if (err) {
- dev_err(dev, "Register IRQ err:%d, msi:%u rsize:%u, nMSI:%u",
- err, msi_index, r->size, gc->num_msix_usable);
+ if (msi_index >= r->size ||
+ msi_index >= gc->num_msix_usable)
+ err = -ENOSPC;
+ else
+ bitmap_set(r->map, msi_index, 1);
- return err;
+ if (err) {
+ dev_err(dev, "Register IRQ err:%d, msi:%u rsize:%u, nMSI:%u",
+ err, msi_index, r->size, gc->num_msix_usable);
+ goto out;
+ }
}
+ queue->eq.msix_index = msi_index;
gic = &gc->irq_contexts[msi_index];
- WARN_ON(gic->handler || gic->arg);
-
- gic->arg = queue;
+ list_add_rcu(&queue->entry, &gic->eq_list);
gic->handler = mana_gd_process_eq_events;
- return 0;
+out:
+ spin_unlock_irqrestore(&r->lock, flags);
+ return err;
}
-static void mana_gd_deregiser_irq(struct gdma_queue *queue)
+static void mana_gd_deregister_irq(struct gdma_queue *queue)
{
struct gdma_dev *gd = queue->gdma_dev;
struct gdma_irq_context *gic;
struct gdma_context *gc;
struct gdma_resource *r;
unsigned int msix_index;
+ struct list_head *p, *n;
+ struct gdma_queue *eq;
unsigned long flags;
gc = gd->gdma_context;
@@ -483,14 +485,23 @@ static void mana_gd_deregiser_irq(struct gdma_queue *queue)
if (WARN_ON(msix_index >= gc->num_msix_usable))
return;
+ spin_lock_irqsave(&r->lock, flags);
+
gic = &gc->irq_contexts[msix_index];
- gic->handler = NULL;
- gic->arg = NULL;
+ list_for_each_safe(p, n, &gic->eq_list) {
+ eq = list_entry(p, struct gdma_queue, entry);
+ if (queue == eq) {
+ list_del(&eq->entry);
+ break;
+ }
+ }
- spin_lock_irqsave(&r->lock, flags);
- bitmap_clear(r->map, msix_index, 1);
- spin_unlock_irqrestore(&r->lock, flags);
+ if (list_empty(&gic->eq_list)) {
+ gic->handler = NULL;
+ bitmap_clear(r->map, msix_index, 1);
+ }
+ spin_unlock_irqrestore(&r->lock, flags);
queue->eq.msix_index = INVALID_PCI_MSIX_INDEX;
}
@@ -553,7 +564,7 @@ static void mana_gd_destroy_eq(struct gdma_context *gc, bool flush_evenets,
dev_warn(gc->dev, "Failed to flush EQ: %d\n", err);
}
- mana_gd_deregiser_irq(queue);
+ mana_gd_deregister_irq(queue);
if (queue->eq.disable_needed)
mana_gd_disable_queue(queue);
@@ -568,7 +579,7 @@ static int mana_gd_create_eq(struct gdma_dev *gd,
u32 log2_num_entries;
int err;
- queue->eq.msix_index = INVALID_PCI_MSIX_INDEX;
+ queue->eq.msix_index = spec->eq.msix_index;
log2_num_entries = ilog2(queue->queue_size / GDMA_EQE_SIZE);
@@ -590,7 +601,8 @@ static int mana_gd_create_eq(struct gdma_dev *gd,
queue->eq.log2_throttle_limit = spec->eq.log2_throttle_limit ?: 1;
if (create_hwq) {
- err = mana_gd_create_hw_eq(gc, queue);
+ err = mana_gd_create_hw_eq(gc, queue,
+ spec->doorbell, spec->pdid);
if (err)
goto out;
@@ -800,6 +812,7 @@ int mana_gd_create_mana_eq(struct gdma_dev *gd,
kfree(queue);
return err;
}
+EXPORT_SYMBOL(mana_gd_create_mana_eq);
int mana_gd_create_mana_wq_cq(struct gdma_dev *gd,
const struct gdma_queue_spec *spec,
@@ -876,6 +889,7 @@ void mana_gd_destroy_queue(struct gdma_context *gc, struct gdma_queue *queue)
mana_gd_free_memory(gmi);
kfree(queue);
}
+EXPORT_SYMBOL(mana_gd_destroy_queue);
int mana_gd_verify_vf_version(struct pci_dev *pdev)
{
@@ -1193,7 +1207,7 @@ static irqreturn_t mana_gd_intr(int irq, void *arg)
struct gdma_irq_context *gic = arg;
if (gic->handler)
- gic->handler(gic->arg);
+ gic->handler(&gic->eq_list);
return IRQ_HANDLED;
}
@@ -1246,7 +1260,7 @@ static int mana_gd_setup_irqs(struct pci_dev *pdev)
for (i = 0; i < nvec; i++) {
gic = &gc->irq_contexts[i];
gic->handler = NULL;
- gic->arg = NULL;
+ INIT_LIST_HEAD(&gic->eq_list);
if (!i)
snprintf(gic->name, MANA_IRQ_NAME_SZ, "mana_hwc@pci:%s",
@@ -1167,6 +1167,9 @@ static int mana_create_eq(struct mana_context *ac)
spec.eq.callback = NULL;
spec.eq.context = ac->eqs;
spec.eq.log2_throttle_limit = LOG2_EQ_THROTTLE;
+ spec.eq.msix_allocated = false;
+ spec.doorbell = gd->doorbell;
+ spec.pdid = gd->pdid;
for (i = 0; i < gc->max_num_queues; i++) {
err = mana_gd_create_mana_eq(gd, &spec, &ac->eqs[i].eq);
@@ -57,6 +57,10 @@ enum gdma_eqe_type {
GDMA_EQE_HWC_INIT_EQ_ID_DB = 129,
GDMA_EQE_HWC_INIT_DATA = 130,
GDMA_EQE_HWC_INIT_DONE = 131,
+
+ /* IB NiC Events start at 176*/
+ GDMA_EQE_SOC_EVENT_NOTIFICATION = 176,
+ GDMA_EQE_SOC_EVENT_TEST,
};
enum {
@@ -291,6 +295,7 @@ struct gdma_queue {
u32 head;
u32 tail;
+ struct list_head entry;
/* Extra fields specific to EQ/CQ. */
union {
@@ -318,6 +323,8 @@ struct gdma_queue_spec {
enum gdma_queue_type type;
bool monitor_avl_buf;
unsigned int queue_size;
+ u32 doorbell;
+ u32 pdid;
/* Extra fields specific to EQ/CQ. */
union {
@@ -326,6 +333,8 @@ struct gdma_queue_spec {
void *context;
unsigned long log2_throttle_limit;
+ bool msix_allocated;
+ unsigned int msix_index;
} eq;
struct {
@@ -341,8 +350,8 @@ struct gdma_queue_spec {
#define MANA_IRQ_NAME_SZ 32
struct gdma_irq_context {
- void (*handler)(void *arg);
- void *arg;
+ void (*handler)(struct list_head *arg);
+ struct list_head eq_list;
char name[MANA_IRQ_NAME_SZ];
};