diff mbox series

mlx5: correct reserved space offset display

Message ID OS3P286MB1640832E1812D661FB81925EFE6F9@OS3P286MB1640.JPNP286.PROD.OUTLOOK.COM (mailing list archive)
State Not Applicable
Headers show
Series mlx5: correct reserved space offset display | expand

Commit Message

Changcheng Liu May 2, 2023, 4:08 p.m. UTC
the reserved_at_xx is start offset of the reserved space, update the
offset display to correct the real offset in the data structure.

Signed-off-by: Liu, Changcheng <changchengx.liu@outlook.com>

Comments

Leon Romanovsky May 3, 2023, 8:14 a.m. UTC | #1
On Wed, May 03, 2023 at 12:08:31AM +0800, Changcheng Liu wrote:
> the reserved_at_xx is start offset of the reserved space, update the
> offset display to correct the real offset in the data structure.
> 
> Signed-off-by: Liu, Changcheng <changchengx.liu@outlook.com>

Thanks for the patch. We are currently in merge window and accept only
urgent fixes. I will take this patch once -rc1 will be released.

Acked-by: Leon Romanovsky <leonro@nvidia.com>
diff mbox series

Patch

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index 66d76e97a087..d8a48e2dd5ec 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -537,7 +537,7 @@  struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 
 	u8         reserved_at_c0[0x10];
 	u8         ipv4_ihl[0x4];
-	u8         reserved_at_c4[0x4];
+	u8         reserved_at_d4[0x4];
 
 	u8         ttl_hoplimit[0x8];
 
@@ -937,7 +937,7 @@  struct mlx5_ifc_e_switch_cap_bits {
 	u8         nvgre_encap_decap[0x1];
 	u8         reserved_at_22[0x1];
 	u8         log_max_fdb_encap_uplink[0x5];
-	u8         reserved_at_21[0x3];
+	u8         reserved_at_28[0x3];
 	u8         log_max_packet_reformat_context[0x5];
 	u8         reserved_2b[0x6];
 	u8         max_encap_header_size[0xa];
@@ -1458,7 +1458,7 @@  enum {
 struct mlx5_ifc_cmd_hca_cap_bits {
 	u8         reserved_at_0[0x10];
 	u8         shared_object_to_user_object_allowed[0x1];
-	u8         reserved_at_13[0xe];
+	u8         reserved_at_11[0xe];
 	u8         vhca_resource_manager[0x1];
 
 	u8         hca_cap_2[0x1];
@@ -1618,7 +1618,7 @@  struct mlx5_ifc_cmd_hca_cap_bits {
 	u8         pci_sync_for_fw_update_event[0x1];
 	u8         reserved_at_1f2[0x6];
 	u8         init2_lag_tx_port_affinity[0x1];
-	u8         reserved_at_1fa[0x3];
+	u8         reserved_at_1f9[0x3];
 	u8         cqe_version[0x4];
 
 	u8         compact_address_vector[0x1];
@@ -1682,9 +1682,9 @@  struct mlx5_ifc_cmd_hca_cap_bits {
 	u8         reserved_at_241[0x9];
 	u8         uar_sz[0x6];
 	u8         port_selection_cap[0x1];
-	u8         reserved_at_248[0x1];
+	u8         reserved_at_251[0x1];
 	u8         umem_uid_0[0x1];
-	u8         reserved_at_250[0x5];
+	u8         reserved_at_253[0x5];
 	u8         log_pg_sz[0x8];
 
 	u8         bf[0x1];
@@ -4062,7 +4062,7 @@  struct mlx5_ifc_mkc_bits {
 
 	u8         reserved_at_1c0[0x19];
 	u8         relaxed_ordering_read[0x1];
-	u8         reserved_at_1d9[0x1];
+	u8         reserved_at_1da[0x1];
 	u8         log_page_size[0x5];
 
 	u8         reserved_at_1e0[0x20];
@@ -5279,7 +5279,7 @@  struct mlx5_ifc_query_special_contexts_out_bits {
 
 	u8	   repeated_mkey[0x20];
 
-	u8         reserved_at_a0[0x20];
+	u8         reserved_at_e0[0x20];
 };
 
 struct mlx5_ifc_query_special_contexts_in_bits {
@@ -11449,9 +11449,9 @@  struct mlx5_ifc_alloc_memic_in_bits {
 	u8         reserved_at_20[0x10];
 	u8         op_mod[0x10];
 
-	u8         reserved_at_30[0x20];
+	u8         reserved_at_40[0x20];
 
-	u8	   reserved_at_40[0x18];
+	u8	   reserved_at_60[0x18];
 	u8	   log_memic_addr_alignment[0x8];
 
 	u8         range_start_addr[0x40];