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[mlx5-next,2/5] net/mlx5: Reliably return TLS device capabilities

Message ID a333ce541fb9497d04126b11c4a0052f9807d141.1649073691.git.leonro@nvidia.com (mailing list archive)
State Accepted
Delegated to: Leon Romanovsky
Headers show
Series Drop Mellanox FPGA TLS support from the kernel | expand

Commit Message

Leon Romanovsky April 4, 2022, 12:08 p.m. UTC 
From: Leon Romanovsky <leonro@nvidia.com>

The capabilities returned from the FW are independent to the compiled
kernel and traditionally rely on the relevant CAPs bit only.

The mlx5_accel_is_ktls_*() functions are compiled out if CONFIG_MLX5_TLS
is not set, which "hides" from the user the information that TLS can be
enabled on this device.

Reviewed-by: Tariq Toukan <tariqt@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
---
 drivers/net/ethernet/mellanox/mlx5/core/fw.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)
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Patch

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw.c b/drivers/net/ethernet/mellanox/mlx5/core/fw.c
index 614687e0e3d9..cfb8bedba512 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/fw.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/fw.c
@@ -35,7 +35,6 @@ 
 #include "mlx5_core.h"
 #include "../../mlxfw/mlxfw.h"
 #include "lib/tout.h"
-#include "accel/tls.h"
 
 enum {
 	MCQS_IDENTIFIER_BOOT_IMG	= 0x1,
@@ -249,7 +248,7 @@  int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
 			return err;
 	}
 
-	if (mlx5_accel_is_ktls_tx(dev) || mlx5_accel_is_ktls_rx(dev)) {
+	if (MLX5_CAP_GEN(dev, tls_tx) || MLX5_CAP_GEN(dev, tls_rx)) {
 		err = mlx5_core_get_caps(dev, MLX5_CAP_TLS);
 		if (err)
 			return err;