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[v2,0/5] clk: renesas: Add GE3D clock/reset entries for RZ/V2H(P) SoC

Message ID 20250309211402.80886-1-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
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Series clk: renesas: Add GE3D clock/reset entries for RZ/V2H(P) SoC | expand

Message

Prabhakar March 9, 2025, 9:13 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series introduces support for enabling PLL clocks in the
RZ/V2H(P) CPG family driver and adds clock and reset entries for the
GE3D module.

v1->v2
- Simplified PLL conf handling as suggested by Geert
- Updated macros to get PLL configuration offsets
- Minor cleanups

Cheers,
Prabhakar

Lad Prabhakar (5):
  clk: renesas: rzv2h: Refactor PLL configuration handling
  clk: renesas: rzv2h: Remove unused `type` field from `struct pll_clk`
  clk: renesas: rzv2h-cpg: Add support for enabling PLLs
  clk: renesas: rzv2h: Rename PLL field macros for consistency
  clk: renesas: r9a09g057: Add clock and reset entries for GE3D

 drivers/clk/renesas/r9a09g047-cpg.c |  2 +-
 drivers/clk/renesas/r9a09g057-cpg.c | 16 +++++-
 drivers/clk/renesas/rzv2h-cpg.c     | 78 +++++++++++++++++++++++------
 drivers/clk/renesas/rzv2h-cpg.h     | 32 +++++++++---
 4 files changed, 104 insertions(+), 24 deletions(-)