[v2,0/2] pinctrl: renesas: Add r8a77995 bias pinconf support

Message

Geert Uytterhoeven June 30, 2021, 2:50 p.m. UTC

Hi all,

This patch series adds a small optimization to R-Car pin bias handling,
and adds bias pinconf support for the R-Car D3 SoC.

Changes compared to v1[1]:
  - Drop all accepted patches,
  - Add [PATCH v2 1/2],
  - Add Reviewed-by,
  - Fix NFRE# and NFWE# handling, now we received confirmation that the
    documentation is correct.

The first patch has been tested on Koelsch and Salvator-XS.
The second patch has been tested on a remote Draak development board by
specifying one of the "bias-{pull-{down,enable},disable}" properties for
the "GP_3_0" and "GP_3_1" pins from DT, and inspecting the impact on the
PUEN2 and PUD2 registers.  Due to the remote setup, actual voltage
levels could not be measured.  Note that enabling pull-down for "GP_3_0"
breaks eMMC operation, as this pin is used as the eMMC's "CMD" signal.

I plan to queue this in renesas-pinctrl for v5.15.

Thanks for your comments!

[1] [PATCH 00/12] pinctrl: renesas: Add more bias pinconf support
    https://lore.kernel.org/linux-renesas-soc/[e-mail]/

Geert Uytterhoeven (2):
  pinctrl: renesas: rcar: Avoid changing PUDn when disabling bias
  pinctrl: renesas: r8a77995: Add bias pinconf support

 drivers/pinctrl/renesas/pfc-r8a77995.c | 320 ++++++++++++++++++++++++-
 drivers/pinctrl/renesas/pinctrl.c      |  16 +-
 drivers/pinctrl/renesas/sh_pfc.h       |   3 +
 3 files changed, 323 insertions(+), 16 deletions(-)