diff mbox series

[v3,03/11] dt-bindings: reset: Document RZ/G2L USBPHY Control bindings

Message ID 20210630073013.22415-4-biju.das.jz@bp.renesas.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series [v3,01/11] dt-bindings: usb: generic-ohci: Document dr_mode property | expand

Commit Message

Biju Das June 30, 2021, 7:30 a.m. UTC 
Add device tree binding document for RZ/G2L USBPHY Control Device.
It mainly controls reset and power down of the USB/PHY.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 v3:
  * New patch.
  * Modelled USBPHY control from phy bindings to reset bindings, since the
    IP mainly contols the reset of USB PHY.     
---
 .../reset/renesas,rzg2l-usbphy-ctrl.yaml      | 66 +++++++++++++++++++
 1 file changed, 66 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml

Comments

Rob Herring July 1, 2021, 2:02 p.m. UTC | #1 
On Wed, 30 Jun 2021 08:30:05 +0100, Biju Das wrote:
> Add device tree binding document for RZ/G2L USBPHY Control Device.
> It mainly controls reset and power down of the USB/PHY.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  v3:
>   * New patch.
>   * Modelled USBPHY control from phy bindings to reset bindings, since the
>     IP mainly contols the reset of USB PHY.
> ---
>  .../reset/renesas,rzg2l-usbphy-ctrl.yaml      | 66 +++++++++++++++++++
>  1 file changed, 66 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.example.dts:19:18: fatal error: dt-bindings/clock/r9a07g044-cpg.h: No such file or directory
   19 |         #include <dt-bindings/clock/r9a07g044-cpg.h>
      |                  ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1416: dt_binding_check] Error 2
\ndoc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1498761

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.
Rob Herring July 1, 2021, 8:23 p.m. UTC | #2 
On Wed, Jun 30, 2021 at 08:30:05AM +0100, Biju Das wrote:
> Add device tree binding document for RZ/G2L USBPHY Control Device.
> It mainly controls reset and power down of the USB/PHY.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  v3:
>   * New patch.
>   * Modelled USBPHY control from phy bindings to reset bindings, since the
>     IP mainly contols the reset of USB PHY.     
> ---
>  .../reset/renesas,rzg2l-usbphy-ctrl.yaml      | 66 +++++++++++++++++++
>  1 file changed, 66 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
> 
> diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
> new file mode 100644
> index 000000000000..2a398c7ce7c8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
> @@ -0,0 +1,66 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L USBPHY Control
> +
> +maintainers:
> +  - Biju Das <biju.das.jz@bp.renesas.com>
> +
> +description:
> +  The RZ/G2L USBPHY Control mainly controls reset and power down of the
> +  USB/PHY.
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
> +      - const: renesas,rzg2l-usbphy-ctrl
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  '#reset-cells':
> +    # see reset.txt in the same directory

Drop the reference. With that,

Reviewed-by: Rob Herring <robh@kernel.org>

> +    const: 1
> +    description: |
> +      The phandle's argument in the reset specifier is the PHY reset associated
> +      with the USB port.
> +      0 = Port 1 Phy reset
> +      1 = Port 2 Phy reset
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - resets
> +  - power-domains
> +  - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> +
> +    phyrst: usbphy-ctrl@11c40000 {
> +        compatible = "renesas,r9a07g044-usbphy-ctrl",
> +                     "renesas,rzg2l-usbphy-ctrl";
> +        reg = <0x11c40000 0x10000>;
> +        clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> +        resets = <&cpg R9A07G044_USB_PRESETN>;
> +        power-domains = <&cpg>;
> +        #reset-cells = <1>;
> +    };
> -- 
> 2.17.1
> 
>
Biju Das July 3, 2021, 10:53 a.m. UTC | #3 
Hi Rob,

Thanks for the feedback.

> Subject: Re: [PATCH v3 03/11] dt-bindings: reset: Document RZ/G2L USBPHY
> Control bindings
> 
> On Wed, Jun 30, 2021 at 08:30:05AM +0100, Biju Das wrote:
> > Add device tree binding document for RZ/G2L USBPHY Control Device.
> > It mainly controls reset and power down of the USB/PHY.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> >  v3:
> >   * New patch.
> >   * Modelled USBPHY control from phy bindings to reset bindings, since
> the
> >     IP mainly contols the reset of USB PHY.
> > ---
> >  .../reset/renesas,rzg2l-usbphy-ctrl.yaml      | 66 +++++++++++++++++++
> >  1 file changed, 66 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.ya
> > ml
> > b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.ya
> > ml
> > new file mode 100644
> > index 000000000000..2a398c7ce7c8
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctr
> > +++ l.yaml
> > @@ -0,0 +1,66 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fschemas%2Freset%2Frenesas%2Crzg2l-usbphy-ctrl.yaml%23&am
> > +p;data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7C770350c845f64b015f680
> > +8d93cce253d%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637607678355
> > +475757%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLC
> > +JBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&amp;sdata=9vEtPav6hmc1axa6Vj2NqT%
> > +2BT0EOoyXTelx2Ft5fCEKE%3D&amp;reserved=0
> > +$schema:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=04%7C01%7Cbiju.das.
> > +jz%40bp.renesas.com%7C770350c845f64b015f6808d93cce253d%7C53d82571da19
> > +47e49cb4625a166a4a2a%7C0%7C0%7C637607678355475757%7CUnknown%7CTWFpbGZ
> > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > +3D%7C1000&amp;sdata=1e4CSqGpir0E%2B7izDrdcuB%2F%2FpL7fqfPNRBPCs0w%2B%
> > +2B84%3D&amp;reserved=0
> > +
> > +title: Renesas RZ/G2L USBPHY Control
> > +
> > +maintainers:
> > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > +
> > +description:
> > +  The RZ/G2L USBPHY Control mainly controls reset and power down of
> > +the
> > +  USB/PHY.
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
> > +      - const: renesas,rzg2l-usbphy-ctrl
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clocks:
> > +    maxItems: 1
> > +
> > +  resets:
> > +    maxItems: 1
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  '#reset-cells':
> > +    # see reset.txt in the same directory
> 
> Drop the reference. With that,

OK. Will drop the reference in next version.

Thanks,
Biju

> 
> Reviewed-by: Rob Herring <robh@kernel.org>
> 
> > +    const: 1
> > +    description: |
> > +      The phandle's argument in the reset specifier is the PHY reset
> associated
> > +      with the USB port.
> > +      0 = Port 1 Phy reset
> > +      1 = Port 2 Phy reset
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - clocks
> > +  - resets
> > +  - power-domains
> > +  - '#reset-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> > +
> > +    phyrst: usbphy-ctrl@11c40000 {
> > +        compatible = "renesas,r9a07g044-usbphy-ctrl",
> > +                     "renesas,rzg2l-usbphy-ctrl";
> > +        reg = <0x11c40000 0x10000>;
> > +        clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
> > +        resets = <&cpg R9A07G044_USB_PRESETN>;
> > +        power-domains = <&cpg>;
> > +        #reset-cells = <1>;
> > +    };
> > --
> > 2.17.1
> >
> >
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
new file mode 100644
index 000000000000..2a398c7ce7c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/renesas,rzg2l-usbphy-ctrl.yaml
@@ -0,0 +1,66 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/renesas,rzg2l-usbphy-ctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L USBPHY Control
+
+maintainers:
+  - Biju Das <biju.das.jz@bp.renesas.com>
+
+description:
+  The RZ/G2L USBPHY Control mainly controls reset and power down of the
+  USB/PHY.
+
+properties:
+  compatible:
+    items:
+      - enum:
+          - renesas,r9a07g044-usbphy-ctrl # RZ/G2{L,LC}
+      - const: renesas,rzg2l-usbphy-ctrl
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  '#reset-cells':
+    # see reset.txt in the same directory
+    const: 1
+    description: |
+      The phandle's argument in the reset specifier is the PHY reset associated
+      with the USB port.
+      0 = Port 1 Phy reset
+      1 = Port 2 Phy reset
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+  - power-domains
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/r9a07g044-cpg.h>
+
+    phyrst: usbphy-ctrl@11c40000 {
+        compatible = "renesas,r9a07g044-usbphy-ctrl",
+                     "renesas,rzg2l-usbphy-ctrl";
+        reg = <0x11c40000 0x10000>;
+        clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
+        resets = <&cpg R9A07G044_USB_PRESETN>;
+        power-domains = <&cpg>;
+        #reset-cells = <1>;
+    };