| Message ID | 20220112174612.10773-24-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add RZ/G2L Display support | expand |
On 1/12/22 8:46 PM, Biju Das wrote: > Add fcpvd node to SoC DTSI. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > index 027b873ea5d3..080b4c8af427 100644 > --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi > @@ -611,6 +611,16 @@ > status = "disabled"; > }; > > + fcpvd0: fcp@10880000 { > + compatible = "renesas,fcpv"; > + reg = <0 0x10880000 0 0x10000>; > + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, > + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, > + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; clock-names? [...] MBR, Sergey
diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 027b873ea5d3..080b4c8af427 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -611,6 +611,16 @@ status = "disabled"; }; + fcpvd0: fcp@10880000 { + compatible = "renesas,fcpv"; + reg = <0 0x10880000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_LCDC_RESET_N>; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g044-cpg"; reg = <0 0x11010000 0 0x10000>;
Add fcpvd node to SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)