| Message ID | 20220824103515.54931-4-wsa+renesas@sang-engineering.com (mailing list archive) |
|---|---|
| State | Rejected |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | r8a779f0: enable MSIOF | expand |
Hi Wolfram, On Wed, Aug 24, 2022 at 12:36 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Thanks for your patch! > --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi > +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi > @@ -101,6 +101,12 @@ &mmc0 { > status = "okay"; > }; > > +&msiof0 { > + pinctrl-0 = <&msiof0_pins>; > + pinctrl-names = "default"; > + status = "okay"; > +}; I assume you added this becomes Spider has an MSIOF pin header? > + > &pfc { > pinctrl-0 = <&scif_clk_pins>; > pinctrl-names = "default"; > @@ -116,6 +122,12 @@ mmc_pins: mmc { > power-source = <1800>; > }; > > + msiof0_pins: msiof0 { > + groups = "msiof0_clk", "msiof0_sync", "msiof0_rxd", > + "msiof0_txd", "msiof0_ss1", "msiof0_ss2"; MSIOF0_SS2 is also used as the VDDQ18_33_SPI voltage selector, which is used as the power source for various components (but not available on the MSIOF0 pin header?), so I'm a but reluctant to add this patch... > + function = "msiof0"; > + }; > + > scif0_pins: scif0 { > groups = "scif0_data", "scif0_ctrl"; > function = "scif0"; Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
Hi Geert, > > +&msiof0 { > > + pinctrl-0 = <&msiof0_pins>; > > + pinctrl-names = "default"; > > + status = "okay"; > > +}; > > I assume you added this becomes Spider has an MSIOF pin header? Yes, that is one reason. It has it on the extension board. On the CPU board, MSIOF0 is also connected to the CPLD. > > + > > &pfc { > > pinctrl-0 = <&scif_clk_pins>; > > pinctrl-names = "default"; > > @@ -116,6 +122,12 @@ mmc_pins: mmc { > > power-source = <1800>; > > }; > > > > + msiof0_pins: msiof0 { > > + groups = "msiof0_clk", "msiof0_sync", "msiof0_rxd", > > + "msiof0_txd", "msiof0_ss1", "msiof0_ss2"; > > MSIOF0_SS2 is also used as the VDDQ18_33_SPI voltage selector, which > is used as the power source for various components (but not available > on the MSIOF0 pin header?), so I'm a but reluctant to add this patch... Uh, you are right with the voltage selector. I missed that, sorry. However, it is present on the MSIOF0 connector at pin 1. My suggestion is to remove SS2 from the PFC node and add a comment describing the situation? All the best, Wolfram
Hi Wolfram, On Mon, Aug 29, 2022 at 1:11 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > > > +&msiof0 { > > > + pinctrl-0 = <&msiof0_pins>; > > > + pinctrl-names = "default"; > > > + status = "okay"; > > > +}; > > > > I assume you added this becomes Spider has an MSIOF pin header? > > Yes, that is one reason. It has it on the extension board. On the CPU > board, MSIOF0 is also connected to the CPLD. > > > > + > > > &pfc { > > > pinctrl-0 = <&scif_clk_pins>; > > > pinctrl-names = "default"; > > > @@ -116,6 +122,12 @@ mmc_pins: mmc { > > > power-source = <1800>; > > > }; > > > > > > + msiof0_pins: msiof0 { > > > + groups = "msiof0_clk", "msiof0_sync", "msiof0_rxd", > > > + "msiof0_txd", "msiof0_ss1", "msiof0_ss2"; > > > > MSIOF0_SS2 is also used as the VDDQ18_33_SPI voltage selector, which > > is used as the power source for various components (but not available > > on the MSIOF0 pin header?), so I'm a but reluctant to add this patch... > > Uh, you are right with the voltage selector. I missed that, sorry. > However, it is present on the MSIOF0 connector at pin 1. My suggestion > is to remove SS2 from the PFC node and add a comment describing the > situation? SS2 is available on the connector, but the power source (VDDQ18_33_SPI) is not. So my preference is to leave MSIOF0 alone. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
> So my preference is to leave MSIOF0 alone.
So, I just resend patch2 with assigned-clocks removed?
Hi Wolfram, On Mon, Aug 29, 2022 at 1:51 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > > So my preference is to leave MSIOF0 alone. > > So, I just resend patch2 with assigned-clocks removed? I think that's the best approach to take. Thanks! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 8075959cccee..f4428a35a548 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -101,6 +101,12 @@ &mmc0 { status = "okay"; }; +&msiof0 { + pinctrl-0 = <&msiof0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; @@ -116,6 +122,12 @@ mmc_pins: mmc { power-source = <1800>; }; + msiof0_pins: msiof0 { + groups = "msiof0_clk", "msiof0_sync", "msiof0_rxd", + "msiof0_txd", "msiof0_ss1", "msiof0_ss2"; + function = "msiof0"; + }; + scif0_pins: scif0 { groups = "scif0_data", "scif0_ctrl"; function = "scif0";
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)