| Message ID | 20220929103043.1228235-3-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | RFC |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add RZ/G2L MTU3 PWM driver | expand |
On Thu, 29 Sep 2022, Biju Das wrote: > Document 16-bit and 32-bit phase counting mode support on > RZ/G2L MTU3 IP. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > * Updated commit header. > --- > .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 35 +++++++++++++++++++ > 1 file changed, 35 insertions(+) Counter binding? > diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > index c1fae8e8d9f9..c4bcf28623d6 100644 > --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > @@ -192,6 +192,37 @@ properties: > "#size-cells": > const: 0 > > +patternProperties: > + "^counter@[1-2]+$": > + type: object > + > + properties: > + compatible: > + const: renesas,rzg2l-mtu3-counter > + > + reg: > + description: Identify counter channels. > + items: > + enum: [ 1, 2 ] > + > + renesas,32bit-phase-counting: > + type: boolean > + description: Enable 32-bit phase counting mode. > + > + renesas,ext-input-phase-clock-select: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + default: 1 > + description: | > + Selects the external clock pin for phase counting mode. > + <0> : MTCLKA and MTCLKB are selected for the external phase clock. > + <1> : MTCLKC and MTCLKD are selected for the external phase clock > + (default) > + > + required: > + - compatible > + - reg > + > required: > - compatible > - reg > @@ -270,6 +301,10 @@ examples: > clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; > power-domains = <&cpg>; > resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; > + counter@1 { > + compatible = "renesas,rzg2l-mtu3-counter"; > + reg = <1>; > + }; > }; > > ...
On Thu, Sep 29, 2022 at 11:30:38AM +0100, Biju Das wrote: > Document 16-bit and 32-bit phase counting mode support on > RZ/G2L MTU3 IP. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > * Updated commit header. > --- > .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 35 +++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > index c1fae8e8d9f9..c4bcf28623d6 100644 > --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > @@ -192,6 +192,37 @@ properties: > "#size-cells": > const: 0 > > +patternProperties: > + "^counter@[1-2]+$": > + type: object > + > + properties: > + compatible: > + const: renesas,rzg2l-mtu3-counter > + > + reg: > + description: Identify counter channels. > + items: > + enum: [ 1, 2 ] > + > + renesas,32bit-phase-counting: > + type: boolean > + description: Enable 32-bit phase counting mode. > + > + renesas,ext-input-phase-clock-select: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + default: 1 > + description: | > + Selects the external clock pin for phase counting mode. > + <0> : MTCLKA and MTCLKB are selected for the external phase clock. > + <1> : MTCLKC and MTCLKD are selected for the external phase clock > + (default) Why do these belong in DT? > + > + required: > + - compatible > + - reg > + > required: > - compatible > - reg > @@ -270,6 +301,10 @@ examples: > clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; > power-domains = <&cpg>; > resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; > + counter@1 { > + compatible = "renesas,rzg2l-mtu3-counter"; > + reg = <1>; > + }; > }; > > ... > -- > 2.25.1 > >
Hi Rob, Thanks for the feedback. > Subject: Re: [PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document > RZ/G2L MTU3 counter > > On Thu, Sep 29, 2022 at 11:30:38AM +0100, Biju Das wrote: > > Document 16-bit and 32-bit phase counting mode support on RZ/G2L > MTU3 > > IP. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > * Updated commit header. > > --- > > .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 35 > +++++++++++++++++++ > > 1 file changed, 35 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > > b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > > index c1fae8e8d9f9..c4bcf28623d6 100644 > > --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > > @@ -192,6 +192,37 @@ properties: > > "#size-cells": > > const: 0 > > > > +patternProperties: > > + "^counter@[1-2]+$": > > + type: object > > + > > + properties: > > + compatible: > > + const: renesas,rzg2l-mtu3-counter > > + > > + reg: > > + description: Identify counter channels. > > + items: > > + enum: [ 1, 2 ] > > + > > + renesas,32bit-phase-counting: > > + type: boolean > > + description: Enable 32-bit phase counting mode. > > + > > + renesas,ext-input-phase-clock-select: > > + $ref: /schemas/types.yaml#/definitions/uint32 > > + enum: [ 0, 1 ] > > + default: 1 > > + description: | > > + Selects the external clock pin for phase counting mode. > > + <0> : MTCLKA and MTCLKB are selected for the external > phase clock. > > + <1> : MTCLKC and MTCLKD are selected for the external > phase clock > > + (default) > > Why do these belong in DT? Hardware supports 4 pins for phase counting mode, MTCLKA Input External clock A input pin (MTU1/MTU2 phase counting mode A phase input) MTCLKB Input External clock B input pin (MTU1/MTU2 phase counting mode B phase input) MTCLKC Input External clock C input pin (MTU2 phase counting mode A phase input) MTCLKD Input External clock D input pin (MTU2 phase counting mode B phase input) For MTU1, it is fixed MTCLKA and MTCLKB. But for MTU2, it can be either 0-{ MTCLKA, MTCLKB} or 1 - { MTCLKC , MTCLKD} On reset it is set to { MTCLKC , MTCLKD}. If user want to change based on board design, they can use this property. Otherwise, runtime using sysfs. If sysfs, do we need to document here? Cheers, Biju > > > > + > > + required: > > + - compatible > > + - reg > > + > > required: > > - compatible > > - reg > > @@ -270,6 +301,10 @@ examples: > > clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; > > power-domains = <&cpg>; > > resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; > > + counter@1 { > > + compatible = "renesas,rzg2l-mtu3-counter"; > > + reg = <1>; > > + }; > > }; > > > > ... > > -- > > 2.25.1 > > > >
Hi Rob, > Subject: RE: [PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document > RZ/G2L MTU3 counter > > Hi Rob, > > Thanks for the feedback. > > > Subject: Re: [PATCH RFC 2/7] dt-bindings: mfd: rzg2l-mtu3: Document > > RZ/G2L MTU3 counter > > > > On Thu, Sep 29, 2022 at 11:30:38AM +0100, Biju Das wrote: > > > Document 16-bit and 32-bit phase counting mode support on RZ/G2L > > MTU3 > > > IP. > > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > > --- > > > * Updated commit header. > > > --- > > > .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 35 > > +++++++++++++++++++ > > > 1 file changed, 35 insertions(+) > > > > > > diff --git > > > a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > > > b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml > > > index c1fae8e8d9f9..c4bcf28623d6 100644 > > > --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l- > mtu3.yaml > > > +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l- > mtu3.yaml > > > @@ -192,6 +192,37 @@ properties: > > > "#size-cells": > > > const: 0 > > > > > > +patternProperties: > > > + "^counter@[1-2]+$": > > > + type: object > > > + > > > + properties: > > > + compatible: > > > + const: renesas,rzg2l-mtu3-counter > > > + > > > + reg: > > > + description: Identify counter channels. > > > + items: > > > + enum: [ 1, 2 ] > > > + > > > + renesas,32bit-phase-counting: > > > + type: boolean > > > + description: Enable 32-bit phase counting mode. > > > + > > > + renesas,ext-input-phase-clock-select: > > > + $ref: /schemas/types.yaml#/definitions/uint32 > > > + enum: [ 0, 1 ] > > > + default: 1 > > > + description: | > > > + Selects the external clock pin for phase counting mode. > > > + <0> : MTCLKA and MTCLKB are selected for the external > > phase clock. > > > + <1> : MTCLKC and MTCLKD are selected for the external > > phase clock > > > + (default) > > > > Why do these belong in DT? > > Hardware supports 4 pins for phase counting mode, > > MTCLKA Input External clock A input pin (MTU1/MTU2 phase counting mode > A phase input) MTCLKB Input External clock B input pin (MTU1/MTU2 > phase counting mode B phase input) MTCLKC Input External clock C input > pin (MTU2 phase counting mode A phase input) MTCLKD Input External > clock D input pin (MTU2 phase counting mode B phase input) > > For MTU1, it is fixed MTCLKA and MTCLKB. > But for MTU2, it can be either 0-{ MTCLKA, MTCLKB} or 1 - { MTCLKC , > MTCLKD} On reset it is set to { MTCLKC , MTCLKD}. > > If user want to change based on board design, they can use this > property. > Otherwise, runtime using sysfs. If sysfs, do we need to document here? As per [1], it is going to be modelled as counter: type: object properties: compatible: const: renesas,rzg2l-mtu3-counter With the following counters taken care internally. count0 :- MTU1 (16-bit phase counting mode) count1 :- MTU2 (16-bit phase counting mode) count2 :- MTU1 + MTU2 (32-bit phase counting mode) and there will be a sysfs property for Selecting the external clock pin for phase counting mode. Is it ok for you? [1] https://lore.kernel.org/linux-renesas-soc/OS0PR01MB59223F69EA3215528519F49086599@OS0PR01MB5922.jpnprd01.prod.outlook.com/T/#m1ee6f933603c7acd480d7652d1ec2e0d9858c842 Cheers, Biju > > > > > > > > > + > > > + required: > > > + - compatible > > > + - reg > > > + > > > required: > > > - compatible > > > - reg > > > @@ -270,6 +301,10 @@ examples: > > > clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; > > > power-domains = <&cpg>; > > > resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; > > > + counter@1 { > > > + compatible = "renesas,rzg2l-mtu3-counter"; > > > + reg = <1>; > > > + }; > > > }; > > > > > > ... > > > -- > > > 2.25.1 > > > > > >
diff --git a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml index c1fae8e8d9f9..c4bcf28623d6 100644 --- a/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml +++ b/Documentation/devicetree/bindings/mfd/renesas,rzg2l-mtu3.yaml @@ -192,6 +192,37 @@ properties: "#size-cells": const: 0 +patternProperties: + "^counter@[1-2]+$": + type: object + + properties: + compatible: + const: renesas,rzg2l-mtu3-counter + + reg: + description: Identify counter channels. + items: + enum: [ 1, 2 ] + + renesas,32bit-phase-counting: + type: boolean + description: Enable 32-bit phase counting mode. + + renesas,ext-input-phase-clock-select: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + default: 1 + description: | + Selects the external clock pin for phase counting mode. + <0> : MTCLKA and MTCLKB are selected for the external phase clock. + <1> : MTCLKC and MTCLKD are selected for the external phase clock + (default) + + required: + - compatible + - reg + required: - compatible - reg @@ -270,6 +301,10 @@ examples: clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; power-domains = <&cpg>; resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; + counter@1 { + compatible = "renesas,rzg2l-mtu3-counter"; + reg = <1>; + }; }; ...
Document 16-bit and 32-bit phase counting mode support on RZ/G2L MTU3 IP. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- * Updated commit header. --- .../bindings/mfd/renesas,rzg2l-mtu3.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+)