diff mbox series

[3/5] arm64: dts: renesas: ebisu: Add RPC HyperFlash device node

Message ID b14c769f62211b67d90dbd2f127357756e6cb4fa.1648548339.git.geert+renesas@glider.be (mailing list archive)
State Mainlined
Commit 5f300a7f3953aea5b2ce996a0bdec31ffd108999
Delegated to: Geert Uytterhoeven
Headers show
Series arm64: dts: renesas: rcar-gen3: Enable HyperFlash support | expand

Commit Message

Geert Uytterhoeven March 29, 2022, 12:20 p.m. UTC 
Add the RPC HyperFlash device node along with its partitions to the
common Ebisu board DTS file.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
 arch/arm64/boot/dts/renesas/ebisu.dtsi | 58 ++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

Comments

Wolfram Sang April 7, 2022, 7:04 a.m. UTC | #1 
On Tue, Mar 29, 2022 at 02:20:03PM +0200, Geert Uytterhoeven wrote:
> Add the RPC HyperFlash device node along with its partitions to the
> common Ebisu board DTS file.
> 
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

Looks sane and builds fine, but I didn't verify the partitions.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi
index 67231c8576c52b18..ae688707f8c69a32 100644
--- a/arch/arm64/boot/dts/renesas/ebisu.dtsi
+++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi
@@ -600,6 +600,12 @@  pwm5_pins: pwm5 {
 		function = "pwm5";
 	};
 
+	rpc_pins: rpc {
+		groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
+			 "rpc_int";
+		function = "rpc";
+	};
+
 	scif2_pins: scif2 {
 		groups = "scif2_data_a";
 		function = "scif2";
@@ -711,6 +717,58 @@  dai0 {
 
 };
 
+&rpc {
+	pinctrl-0 = <&rpc_pins>;
+	pinctrl-names = "default";
+
+	/* Left disabled.  To be enabled by firmware when unlocked. */
+
+	flash@0 {
+		compatible = "cypress,hyperflash", "cfi-flash";
+		reg = <0>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			bootparam@0 {
+				reg = <0x00000000 0x040000>;
+				read-only;
+			};
+			bl2@40000 {
+				reg = <0x00040000 0x140000>;
+				read-only;
+			};
+			cert_header_sa6@180000 {
+				reg = <0x00180000 0x040000>;
+				read-only;
+			};
+			bl31@1c0000 {
+				reg = <0x001c0000 0x040000>;
+				read-only;
+			};
+			tee@200000 {
+				reg = <0x00200000 0x440000>;
+				read-only;
+			};
+			uboot@640000 {
+				reg = <0x00640000 0x100000>;
+				read-only;
+			};
+			dtb@740000 {
+				reg = <0x00740000 0x080000>;
+			};
+			kernel@7c0000 {
+				reg = <0x007c0000 0x1400000>;
+			};
+			user@1bc0000 {
+				reg = <0x01bc0000 0x2440000>;
+			};
+		};
+	};
+};
+
 &rwdt {
 	timeout-sec = <60>;
 	status = "okay";