[v3,0/8] Various SMP related fixes

Message

Atish Patra Feb. 8, 2019, 1:51 a.m. UTC

The existing upstream kernel doesn't boot for non-smp
configuration. This patch series address various issues
with non-smp configurations.

The patch series is based on 5.0-rc5. Tested on QEMU and
HiFive Unleashed board using both OpenSBI & BBL.

Changes from v2->v3

1. Fixed spurious white space.
2. Added lockdep for smpboot completion variable.
2. Added a sanity check for hwcap.

Changes from v1->v2

1. Move the cpuid to hartd id map to smp.c from setup.c
2. Split 3rd patch into several small patches based on
   logical grouping.
3. Added a new patch that fixes an issue in hwcap query.
4. Changed the title of the patch series.

Atish Patra (8):
RISC-V: Do not wait indefinitely in __cpu_up
RISC-V: Move cpuid to hartid mapping to SMP.
RISC-V: Remove NR_CPUs check during hartid search from DT
RISC-V: Allow hartid-to-cpuid function to fail.
RISC-V: Compare cpuid with NR_CPUS before mapping.
clocksource/drivers/riscv: Add required checks during clock source
init
irqchip/irq-sifive-plic:: Check and continue in case of an invalid
cpuid.
RISC-V: Assign hwcap only according to boot cpu.

arch/riscv/include/asm/smp.h      | 14 ++++++++---
arch/riscv/kernel/cpu.c           |  4 ---
arch/riscv/kernel/cpufeature.c    | 52 +++++++++++++++++++++++++++------------
arch/riscv/kernel/setup.c         |  9 -------
arch/riscv/kernel/smp.c           | 10 +++++++-
arch/riscv/kernel/smpboot.c       | 20 ++++++++++++---
drivers/clocksource/timer-riscv.c | 23 ++++++++++++++---
drivers/irqchip/irq-sifive-plic.c |  5 ++++
8 files changed, 98 insertions(+), 39 deletions(-)

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2.7.4