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[v3,0/2] riscv: sifive_l2_cache: Add support for SiFive FU740 SoC

Message ID 1607596083-81480-1-git-send-email-yash.shah@sifive.com (mailing list archive)
Headers show
Series riscv: sifive_l2_cache: Add support for SiFive FU740 SoC | expand

Message

Yash Shah Dec. 10, 2020, 10:28 a.m. UTC 
Add support for additional interrupt present in SiFive FU740 chip.

Changes:
v3:
- Rename the subject line of dt-binding patch
- Add the additional interrupt "DirFail" as the last entry so as to keep
  the order of all previous index same.

v2:
- Changes as per Rob Herring's request on v1

Yash Shah (2):
  dt-bindings: riscv: Update l2 cache DT documentation to add support
    for SiFive FU740
  RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive
    FU740

 .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 +++++++++++++++++++---
 drivers/soc/sifive/sifive_l2_cache.c               | 27 +++++++++++++++--
 2 files changed, 54 insertions(+), 7 deletions(-)

Comments

Palmer Dabbelt Jan. 8, 2021, 1:36 a.m. UTC | #1 
On Thu, 10 Dec 2020 02:28:01 PST (-0800), yash.shah@sifive.com wrote:
> Add support for additional interrupt present in SiFive FU740 chip.
>
> Changes:
> v3:
> - Rename the subject line of dt-binding patch
> - Add the additional interrupt "DirFail" as the last entry so as to keep
>   the order of all previous index same.
>
> v2:
> - Changes as per Rob Herring's request on v1
>
> Yash Shah (2):
>   dt-bindings: riscv: Update l2 cache DT documentation to add support
>     for SiFive FU740
>   RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive
>     FU740
>
>  .../devicetree/bindings/riscv/sifive-l2-cache.yaml | 34 +++++++++++++++++++---
>  drivers/soc/sifive/sifive_l2_cache.c               | 27 +++++++++++++++--
>  2 files changed, 54 insertions(+), 7 deletions(-)

Thanks, these are on for-next.