Message ID | 20190617185920.29581-1-atish.patra@wdc.com (mailing list archive) |
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Headers | show
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18 Jun 2019 02:59:56 +0800 IronPort-SDR: Ud8on+IaMVIIUVjByxdNoKU18mrGM3M5wfD+he5Kio+keycg/cF8KClDFD8tdGNfPCrlU+8DZu cVT40pzz9fvcJ1BkSvTleMlggtGl8mXqZPe82e05FiIPylExDKrlsMUT2Q89C32/dTKp8IpMQU jR5cXs3XxXkxqi/GgTXe0I5bnJZciyoCM4WTP6xC0Cb3q7O/uUFfZXxy8gh434FHL+XQ8p2svp Rf7RTg4auNMwn23j6+zAvS6LZLhNEAIPGh+CQi4r2B6EFyXC4YbRa8cJsKITQ4dadSxsWyQWPd 8zHEdcsFwQ01mfdVIcLWrn0z Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep02.wdc.com with ESMTP; 17 Jun 2019 11:59:26 -0700 IronPort-SDR: rf9zdZSYllUoDZSjIGKlJyFrk3+jHCW0uMuhJDcO3oUablZz06zS5vUYxDAc1e5wHt0RVBa1Yj vpJC9lvyV0577zFg84pDpuJ4wLIPPVz9YQY5yIAdeGL7rU3pOU80+hl6B4jfSVaHG3H8svdDMg ROnzXWVSVLq7HPYqWwNVwVHbXwHziHw5B0DydW3hbiCAT+C+dnKVqqthxRyUKywWtqHTgHB8bb lrs3Rjkz9SwyIjaR4F6FZyLZSlm0I1/K9xL+82zj/gud4kvW0R7yiaiLVQ/XaOzNxTMue+7nE/ /OQ= Received: from jedi-01.sdcorp.global.sandisk.com (HELO jedi-01.int.fusionio.com) ([10.11.143.218]) by uls-op-cesaip01.wdc.com with ESMTP; 17 Jun 2019 11:59:54 -0700 From: Atish Patra <atish.patra@wdc.com> To: linux-kernel@vger.kernel.org Subject: [PATCH v7 0/7] Unify CPU topology across ARM & RISC-V Date: Mon, 17 Jun 2019 11:59:13 -0700 Message-Id: <20190617185920.29581-1-atish.patra@wdc.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190617_120003_253062_5199DE73 X-CRM114-Status: GOOD ( 17.50 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: <linux-riscv.lists.infradead.org> List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-riscv>, <mailto:linux-riscv-request@lists.infradead.org?subject=unsubscribe> List-Archive: <http://lists.infradead.org/pipermail/linux-riscv/> List-Post: <mailto:linux-riscv@lists.infradead.org> List-Help: <mailto:linux-riscv-request@lists.infradead.org?subject=help> List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-riscv>, <mailto:linux-riscv-request@lists.infradead.org?subject=subscribe> Cc: Mark Rutland <mark.rutland@arm.com>, "Rafael J. Wysocki" <rafael@kernel.org>, "Peter Zijlstra \(Intel\)" <peterz@infradead.org>, Catalin Marinas <catalin.marinas@arm.com>, Linus Walleij <linus.walleij@linaro.org>, Palmer Dabbelt <palmer@sifive.com>, Will Deacon <will.deacon@arm.com>, Richard Fontana <rfontana@redhat.com>, Mauro Carvalho Chehab <mchehab+samsung@kernel.org>, linux-riscv@lists.infradead.org, Ingo Molnar <mingo@kernel.org>, Anup Patel <anup@brainfault.org>, Russell King <linux@armlinux.org.uk>, Morten Rasmussen <morten.rasmussen@arm.com>, devicetree@vger.kernel.org, Albert Ou <aou@eecs.berkeley.edu>, Rob Herring <robh+dt@kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Jonathan Cameron <Jonathan.Cameron@huawei.com>, Thomas Gleixner <tglx@linutronix.de>, linux-arm-kernel@lists.infradead.org, Atish Patra <atish.patra@wdc.com>, Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Jeremy Linton <jeremy.linton@arm.com>, Otto Sabart <ottosabart@seberm.com>, Sudeep Holla <sudeep.holla@arm.com>, "David S. Miller" <davem@davemloft.net> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org X-Virus-Scanned: ClamAV using ClamSMTP |
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Unify CPU topology across ARM & RISC-V
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The cpu-map DT entry in ARM can describe the CPU topology in much better way compared to other existing approaches. RISC-V can easily adopt this binding to represent its own CPU topology. Thus, both cpu-map DT binding and topology parsing code can be moved to a common location so that RISC-V or any other architecture can leverage that. The relevant discussion regarding unifying cpu topology can be found in [1]. arch_topology seems to be a perfect place to move the common code. I have not introduced any significant functional changes in the moved code. The only downside in this approach is that the capacity code will be executed for RISC-V as well. But, it will exit immediately after not able to find the appropriate DT node. If the overhead is considered too much, we can always compile out capacity related functions under a different config for the architectures that do not support them. There was an opportunity to unify topology data structure for ARM32 done by patch 3/4. But, I refrained from making any other changes as I am not very well versed with original intention for some functions that are present in arch_topology.c. I hope this patch series can be served as a baseline for such changes in the future. The patches have been tested for RISC-V and compile tested for ARM64, ARM32 & x86. From Jeremy, "I applied these to 5.2rc2, along with my PPTT/MT change and verified the system & scheduler topology/etc on DAWN and ThunderX2 using ACPI on arm64. They appear to be working correctly. so for the series, Tested-by: Jeremy Linton <jeremy.linton@arm.com>" The socket change[2] is also now part of this series. [1] https://lkml.org/lkml/2018/11/6/19 [2] https://lkml.org/lkml/2018/11/7/918 QEMU changes for RISC-V topology are available at https://github.com/atishp04/qemu/tree/riscv_topology_dt HiFive Unleashed DT with topology node is available here. https://github.com/atishp04/opensbi/tree/HiFive_unleashed_topology It can be verified with OpenSBI with following additional compile time option. FW_PAYLOAD_FDT="unleashed_topology.dtb" Changes from v6->v7 1. Added socket to HiFive Unleashed topology example. 2. Added Acked-by & Reviewed-by. Changes from v5->v6 1. Added two more patches from Sudeep about maintainership of arch_topology.c and Kconfig update. 2. Added Tested-by & Reviewed-by 3. Fixed a nit (reordering of variables) Changes from v4-v5 1. Removed the arch_topology.h header inclusion from topology.c and arch_topology.c file. Added it in linux/topology.h. 2. core_id is set to -1 upon reset. Otherwise, ARM topology store function does not work. Changes from v3->v4 1. Get rid of ARM32 specific information in topology structure. 2. Remove redundant functions from ARM32 and use common code instead. Changes from v2->v3 1. Cover letter update with experiment DT for topology changes. 2. Added the patch for [2]. Changes from v1->v2 1. ARM32 can now use the common code as well. Atish Patra (4): dt-binding: cpu-topology: Move cpu-map to a common binding. cpu-topology: Move cpu topology code to common code. arm: Use common cpu_topology structure and functions. RISC-V: Parse cpu topology during boot. Sudeep Holla (3): Documentation: DT: arm: add support for sockets defining package boundaries base: arch_topology: update Kconfig help description MAINTAINERS: Add an entry for generic architecture topology .../topology.txt => cpu/cpu-topology.txt} | 136 ++++++-- MAINTAINERS | 7 + arch/arm/include/asm/topology.h | 20 -- arch/arm/kernel/topology.c | 60 +--- arch/arm64/include/asm/topology.h | 23 -- arch/arm64/kernel/topology.c | 303 +----------------- arch/riscv/Kconfig | 1 + arch/riscv/kernel/smpboot.c | 3 + drivers/base/Kconfig | 2 +- drivers/base/arch_topology.c | 298 +++++++++++++++++ include/linux/arch_topology.h | 26 ++ include/linux/topology.h | 1 + 12 files changed, 454 insertions(+), 426 deletions(-) rename Documentation/devicetree/bindings/{arm/topology.txt => cpu/cpu-topology.txt} (66%) -- 2.21.0