[0/2] riscv: Align shared mappings to avoid cache aliasing

Message

Marc Gauthier Nov. 15, 2019, 7:23 p.m. UTC

Ensure optimal performance on larger VIPT caches by aligning shared
mappings to the maximum cache "span" (line size * number of sets) of
all CPU L1 instruction and data caches (L2 and up are rarely VIPT).
If the device tree does not provide cache parameters, use a conservative
16 KB alignment:  only large enough to avoid aliasing in most VIPT caches.

Tested on Linux 5.4-rc7 in simulation.

Signed-off-by: Marc Gauthier <[e-mail]>

Marc Gauthier (2):
  riscv: Align shared mappings to SHMLBA
  riscv: Set SHMLBA according to cache geometry

 arch/riscv/include/asm/pgtable.h  |   4 ++
 arch/riscv/include/asm/shmparam.h |  12 ++++
 arch/riscv/kernel/cacheinfo.c     |  49 +++++++++++++
 arch/riscv/kernel/sys_riscv.c     | 112 ++++++++++++++++++++++++++++++
 4 files changed, 177 insertions(+)
 create mode 100644 arch/riscv/include/asm/shmparam.h