[v2,0/2] riscv: Align shared mappings to avoid cache aliasing

Message ID	20191126224446.15145-1-consult-mg@gstardust.com (mailing list archive)
Headers	show Return-Path: <SRS0=CG02=ZS=lists.infradead.org=linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A276220722 From: Marc Gauthier <consult-mg@gstardust.com> To: linux-riscv@lists.infradead.org Subject: [PATCH v2 0/2] riscv: Align shared mappings to avoid cache aliasing Date: Tue, 26 Nov 2019 17:44:44 -0500 Message-Id: <20191126224446.15145-1-consult-mg@gstardust.com> summary: Content analysis details: (-0.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at https://www.dnswl.org/, low trust [64.147.123.19 listed in list.dnswl.org] -0.0 SPF_HELO_PASS SPF: HELO matches SPF record 0.0 SPF_NONE SPF: sender does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain Precedence: list Cc: Marc Gauthier <consult-mg@gstardust.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Paul Walmsley <paul.walmsley@sifive.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+patchwork-linux-riscv=patchwork.kernel.org@lists.infradead.org
Series	riscv: Align shared mappings to avoid cache aliasing \| expand [v2,0/2] riscv: Align shared mappings to avoid cache aliasing [v2,1/2] riscv: Align shared mappings to SHMLBA [v2,2/2] riscv: Set SHMLBA according to cache geometry

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20191126224446.15145-1-consult-mg@gstardust.com (mailing list archive)

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DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A276220722
From: Marc Gauthier <consult-mg@gstardust.com>
To: linux-riscv@lists.infradead.org
Subject: [PATCH v2 0/2] riscv: Align shared mappings to avoid cache aliasing
Date: Tue, 26 Nov 2019 17:44:44 -0500
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 Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>,
 Paul Walmsley <paul.walmsley@sifive.com>
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Series

riscv: Align shared mappings to avoid cache aliasing | expand

Message

Marc Gauthier Nov. 26, 2019, 10:44 p.m. UTC

Ensure optimal performance on larger VIPT caches by aligning shared
mappings to the maximum cache "span" (line size * number of sets) of
all CPU L1 instruction and data caches (L2 and up are rarely VIPT).
If the device tree does not provide cache parameters, use a conservative
16 KB alignment:  only large enough to avoid aliasing in most VIPT caches.

This patchset is based on Linux 5.4-rc7 and tested in simulation.

Changes in v2:
- Fix formatting per scripts/checkpatch.pl
- Edit include/asm/Kbuild to reflect shmparam.h addition

Signed-off-by: Marc Gauthier <consult-mg@gstardust.com>

Marc Gauthier (2):
  riscv: Align shared mappings to SHMLBA
  riscv: Set SHMLBA according to cache geometry

 arch/riscv/include/asm/Kbuild     |   1 -
 arch/riscv/include/asm/pgtable.h  |   4 ++
 arch/riscv/include/asm/shmparam.h |  12 ++++
 arch/riscv/kernel/cacheinfo.c     |  52 ++++++++++++++
 arch/riscv/kernel/sys_riscv.c     | 113 ++++++++++++++++++++++++++++++
 5 files changed, 181 insertions(+), 1 deletion(-)
 create mode 100644 arch/riscv/include/asm/shmparam.h