| Message ID | 20200318011144.91532-1-atish.patra@wdc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add support for SBI v0.2 and CPU hotplug | expand |
Hi Atish, On Wed, 18 Mar 2020 at 02:12, Atish Patra <atish.patra@wdc.com> wrote: > > The Supervisor Binary Interface(SBI) specification[1] now defines a > base extension that provides extendability to add future extensions > while maintaining backward compatibility with previous versions. > The new version is defined as 0.2 and older version is marked as 0.1. > > This series adds following features to RISC-V Linux. > 1. Adds support for SBI v0.2 > 2. A Unified calling convention implementation between 0.1 and 0.2. > 3. SBI Hart state management extension (HSM) > 4. Ordered booting of harts > 4. CPU hotplug If it's any help I tried this series with both OpenSBI v0.6 and master (9a74a64ae08), and in both cases Linux found all four cpus. I can test the hotplug stuff too if you send me instructions. In any case you can add my Tested-by: Emil Renner Berthing <kernel@esmil.dk> /Emil
On Sun, Mar 22, 2020 at 10:49 AM Emil Renner Berthing <emil.renner.berthing@gmail.com> wrote: > > Hi Atish, > > On Wed, 18 Mar 2020 at 02:12, Atish Patra <atish.patra@wdc.com> wrote: > > > > The Supervisor Binary Interface(SBI) specification[1] now defines a > > base extension that provides extendability to add future extensions > > while maintaining backward compatibility with previous versions. > > The new version is defined as 0.2 and older version is marked as 0.1. > > > > This series adds following features to RISC-V Linux. > > 1. Adds support for SBI v0.2 > > 2. A Unified calling convention implementation between 0.1 and 0.2. > > 3. SBI Hart state management extension (HSM) > > 4. Ordered booting of harts > > 4. CPU hotplug > > If it's any help I tried this series with both OpenSBI v0.6 and master > (9a74a64ae08), > and in both cases Linux found all four cpus. I can test the hotplug > stuff too if you send > me instructions. In any case you can add my > > Tested-by: Emil Renner Berthing <kernel@esmil.dk> > Thanks for testing the patches. Here are the steps to online/offline a cpu. To mark a cpu offline $echo 0 > /sys/devices/system/cpu/cpuX/online To mark a cpu online $echo 1 > /sys/devices/system/cpu/cpuX/online Here are the official kernel documentation. https://www.kernel.org/doc/html/latest/core-api/cpu_hotplug.html > /Emil >
On Tue, 17 Mar 2020 18:11:33 PDT (-0700), Atish Patra wrote: > The Supervisor Binary Interface(SBI) specification[1] now defines a > base extension that provides extendability to add future extensions > while maintaining backward compatibility with previous versions. > The new version is defined as 0.2 and older version is marked as 0.1. While 0.2 isn't official, I don't think we got any comments on 0.2-rc1 so let's just go ahead and release it. I'm hoping to send my PR at the end of the week, I'll be sure to tag 0.2 before then -- things are still a bit of a mess here due to the internet issues, but I've got a bunch of networking gear coming this week so hopefully it'll get better... Thanks for this! > > This series adds following features to RISC-V Linux. > 1. Adds support for SBI v0.2 > 2. A Unified calling convention implementation between 0.1 and 0.2. > 3. SBI Hart state management extension (HSM) > 4. Ordered booting of harts > 4. CPU hotplug > > Dependencies: > The support for SBI v0.2 and HSM extension is already available in OpenSBI > master. > > [1] https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc > > The patches are also available in following github repositery. > > Linux Kernel: https://github.com/atishp04/linux/tree/sbi_v0.2_v11 > > Patches 1-5 implements the SBI v0.2 and unified calling convention. > Patches 6-7 adds a cpu_ops method that allows different booting protocols > dynamically. > Patches 9-10 adds HSM extension and ordered hart booting support. > Patche 11 adds cpu hotplug support. > > Changes v10->v11: > 1. Addressed few nitpick comments. > 2. Dropped plic patch as it is taken through IRQ tree. > > Changes from v9->10: > 1. Minor copyright fixes. > 2. Renaming of HSM extension definitions to match the spec. > > Changes from v8->v9: > 1. Added a sliding window hart base method to support larger hart masks. > 2. Added a callback to disable interrupts when cpu go offline. > 3. Made the HSM extension series more modular. > > Changes from v7-v8: > 1. Refactored to code to have modular cpu_ops calls. > 2. Refactored HSM extension from sbi.c to cpu_ops_sbi.c. > 3. Fix plic driver to handle cpu hotplug. > > Changes from v6-v7: > 1. Rebased on v5.5 > 2. Fixed few compilation issues for !CONFIG_SMP and !CONFIG_RISCV_SBI > 3. Added SBI HSM extension > 4. Add CPU hotplug support > > Changes from v5->v6 > 1. Fixed few compilation issues around config. > 2. Fixed hart mask generation issues for RFENCE & IPI extensions. > > Changes from v4->v5 > 1. Fixed few minor comments related to static & inline. > 2. Make sure that every patch is boot tested individually. > > Changes from v3->v4. > 1. Rebased on for-next. > 2. Fixed issuses with checkpatch --strict. > 3. Unfied all IPI/fence related functions. > 4. Added Hfence related SBI calls. > > Changes from v2->v3. > 1. Moved v0.1 extensions to a new config. > 2. Added support for relacement extensions of v0.1 extensions. > > Changes from v1->v2 > 1. Removed the legacy calling convention. > 2. Moved all SBI related calls to sbi.c. > 3. Moved all SBI related macros to uapi. > > Atish Patra (11): > RISC-V: Mark existing SBI as 0.1 SBI. > RISC-V: Add basic support for SBI v0.2 > RISC-V: Add SBI v0.2 extension definitions > RISC-V: Introduce a new config for SBI v0.1 > RISC-V: Implement new SBI v0.2 extensions > RISC-V: Move relocate and few other functions out of __init > RISC-V: Add cpu_ops and modify default booting method > RISC-V: Export SBI error to linux error mapping function > RISC-V: Add SBI HSM extension definitions > RISC-V: Add supported for ordered booting method using HSM > RISC-V: Support cpu hotplug > > arch/riscv/Kconfig | 19 +- > arch/riscv/include/asm/cpu_ops.h | 46 +++ > arch/riscv/include/asm/sbi.h | 195 +++++---- > arch/riscv/include/asm/smp.h | 24 ++ > arch/riscv/kernel/Makefile | 6 + > arch/riscv/kernel/cpu-hotplug.c | 87 ++++ > arch/riscv/kernel/cpu_ops.c | 46 +++ > arch/riscv/kernel/cpu_ops_sbi.c | 115 ++++++ > arch/riscv/kernel/cpu_ops_spinwait.c | 43 ++ > arch/riscv/kernel/head.S | 179 +++++---- > arch/riscv/kernel/sbi.c | 575 ++++++++++++++++++++++++++- > arch/riscv/kernel/setup.c | 24 +- > arch/riscv/kernel/smpboot.c | 53 ++- > arch/riscv/kernel/traps.c | 2 +- > arch/riscv/kernel/vmlinux.lds.S | 5 +- > 15 files changed, 1249 insertions(+), 170 deletions(-) > create mode 100644 arch/riscv/include/asm/cpu_ops.h > create mode 100644 arch/riscv/kernel/cpu-hotplug.c > create mode 100644 arch/riscv/kernel/cpu_ops.c > create mode 100644 arch/riscv/kernel/cpu_ops_sbi.c > create mode 100644 arch/riscv/kernel/cpu_ops_spinwait.c
On Tue, 2020-03-31 at 11:35 -0700, Palmer Dabbelt wrote: > On Tue, 17 Mar 2020 18:11:33 PDT (-0700), Atish Patra wrote: > > The Supervisor Binary Interface(SBI) specification[1] now defines a > > base extension that provides extendability to add future extensions > > while maintaining backward compatibility with previous versions. > > The new version is defined as 0.2 and older version is marked as > > 0.1. > > While 0.2 isn't official, I don't think we got any comments on 0.2- > rc1 so let's > just go ahead and release it. I'm hoping to send my PR at the end of > the week, > I'll be sure to tag 0.2 before then -- things are still a bit of a > mess here > due to the internet issues, but I've got a bunch of networking gear > coming this > week so hopefully it'll get better... > Awesome. Thanks! > Thanks for this! > > > This series adds following features to RISC-V Linux. > > 1. Adds support for SBI v0.2 > > 2. A Unified calling convention implementation between 0.1 and 0.2. > > 3. SBI Hart state management extension (HSM) > > 4. Ordered booting of harts > > 4. CPU hotplug > > > > Dependencies: > > The support for SBI v0.2 and HSM extension is already available in > > OpenSBI > > master. > > > > [1] > > https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc > > > > The patches are also available in following github repositery. > > > > Linux Kernel: https://github.com/atishp04/linux/tree/sbi_v0.2_v11 > > > > Patches 1-5 implements the SBI v0.2 and unified calling convention. > > Patches 6-7 adds a cpu_ops method that allows different booting > > protocols > > dynamically. > > Patches 9-10 adds HSM extension and ordered hart booting support. > > Patche 11 adds cpu hotplug support. > > > > Changes v10->v11: > > 1. Addressed few nitpick comments. > > 2. Dropped plic patch as it is taken through IRQ tree. > > > > Changes from v9->10: > > 1. Minor copyright fixes. > > 2. Renaming of HSM extension definitions to match the spec. > > > > Changes from v8->v9: > > 1. Added a sliding window hart base method to support larger hart > > masks. > > 2. Added a callback to disable interrupts when cpu go offline. > > 3. Made the HSM extension series more modular. > > > > Changes from v7-v8: > > 1. Refactored to code to have modular cpu_ops calls. > > 2. Refactored HSM extension from sbi.c to cpu_ops_sbi.c. > > 3. Fix plic driver to handle cpu hotplug. > > > > Changes from v6-v7: > > 1. Rebased on v5.5 > > 2. Fixed few compilation issues for !CONFIG_SMP and > > !CONFIG_RISCV_SBI > > 3. Added SBI HSM extension > > 4. Add CPU hotplug support > > > > Changes from v5->v6 > > 1. Fixed few compilation issues around config. > > 2. Fixed hart mask generation issues for RFENCE & IPI extensions. > > > > Changes from v4->v5 > > 1. Fixed few minor comments related to static & inline. > > 2. Make sure that every patch is boot tested individually. > > > > Changes from v3->v4. > > 1. Rebased on for-next. > > 2. Fixed issuses with checkpatch --strict. > > 3. Unfied all IPI/fence related functions. > > 4. Added Hfence related SBI calls. > > > > Changes from v2->v3. > > 1. Moved v0.1 extensions to a new config. > > 2. Added support for relacement extensions of v0.1 extensions. > > > > Changes from v1->v2 > > 1. Removed the legacy calling convention. > > 2. Moved all SBI related calls to sbi.c. > > 3. Moved all SBI related macros to uapi. > > > > Atish Patra (11): > > RISC-V: Mark existing SBI as 0.1 SBI. > > RISC-V: Add basic support for SBI v0.2 > > RISC-V: Add SBI v0.2 extension definitions > > RISC-V: Introduce a new config for SBI v0.1 > > RISC-V: Implement new SBI v0.2 extensions > > RISC-V: Move relocate and few other functions out of __init > > RISC-V: Add cpu_ops and modify default booting method > > RISC-V: Export SBI error to linux error mapping function > > RISC-V: Add SBI HSM extension definitions > > RISC-V: Add supported for ordered booting method using HSM > > RISC-V: Support cpu hotplug > > > > arch/riscv/Kconfig | 19 +- > > arch/riscv/include/asm/cpu_ops.h | 46 +++ > > arch/riscv/include/asm/sbi.h | 195 +++++---- > > arch/riscv/include/asm/smp.h | 24 ++ > > arch/riscv/kernel/Makefile | 6 + > > arch/riscv/kernel/cpu-hotplug.c | 87 ++++ > > arch/riscv/kernel/cpu_ops.c | 46 +++ > > arch/riscv/kernel/cpu_ops_sbi.c | 115 ++++++ > > arch/riscv/kernel/cpu_ops_spinwait.c | 43 ++ > > arch/riscv/kernel/head.S | 179 +++++---- > > arch/riscv/kernel/sbi.c | 575 > > ++++++++++++++++++++++++++- > > arch/riscv/kernel/setup.c | 24 +- > > arch/riscv/kernel/smpboot.c | 53 ++- > > arch/riscv/kernel/traps.c | 2 +- > > arch/riscv/kernel/vmlinux.lds.S | 5 +- > > 15 files changed, 1249 insertions(+), 170 deletions(-) > > create mode 100644 arch/riscv/include/asm/cpu_ops.h > > create mode 100644 arch/riscv/kernel/cpu-hotplug.c > > create mode 100644 arch/riscv/kernel/cpu_ops.c > > create mode 100644 arch/riscv/kernel/cpu_ops_sbi.c > > create mode 100644 arch/riscv/kernel/cpu_ops_spinwait.c