| Message ID | 20200603081104.14004-1-alex@ghiti.fr (mailing list archive) |
|---|---|
| Headers | show |
| Series | Introduce sv48 support | expand |
Hi Palmer, Le 6/3/20 à 4:10 AM, Alexandre Ghiti a écrit : > This patchset implements sv48 support at runtime. The kernel will try to > boot with 4-level page table and will fallback to 3-level if the HW does not > support it. > > The biggest advantage is that we only have one kernel for 64bit, which > is way easier to maintain. > > Folding the 4th level into a 3-level page table has almost no cost at > runtime. But as mentioned Palmer, the relocatable code generated is less > performant. > > At the moment, there is no way to build a 3-level page table non-relocatable > 64bit kernel. We agreed that distributions will use this runtime configuration > anyway, but Palmer proposed to introduce a new Kconfig, which I will do later > as sv48 support was asked for 5.8. > > Finally, the user can now ask for sv39 explicitly by using the device-tree > which will reduce memory footprint and reduce the number of memory accesses > in case of TLB miss. > > Changes in v2: > * Move variable declarations to pgtable.h in patch 5/7 as suggested by Anup > * Restore mmu-type properties in patch 6 as suggested by Anup > * Fix unused variable in patch 5 that was used in patch 6 > * Fix SPARSEMEM build (patch 2 was modified so I dropped the Reviewed-by) > * Applied various Reviewed-by > > Alexandre Ghiti (8): > riscv: Get rid of compile time logic with MAX_EARLY_MAPPING_SIZE > riscv: Allow to dynamically define VA_BITS > riscv: Simplify MAXPHYSMEM config > riscv: Prepare ptdump for vm layout dynamic addresses > riscv: Implement sv48 support > riscv: Allow user to downgrade to sv39 when hw supports sv48 > riscv: Use pgtable_l4_enabled to output mmu type in cpuinfo > riscv: Explicit comment about user virtual address space size > > arch/riscv/Kconfig | 34 ++--- > arch/riscv/include/asm/csr.h | 3 +- > arch/riscv/include/asm/fixmap.h | 1 + > arch/riscv/include/asm/page.h | 15 +++ > arch/riscv/include/asm/pgalloc.h | 36 ++++++ > arch/riscv/include/asm/pgtable-64.h | 97 +++++++++++++- > arch/riscv/include/asm/pgtable.h | 31 ++++- > arch/riscv/include/asm/sparsemem.h | 6 +- > arch/riscv/kernel/cpu.c | 23 ++-- > arch/riscv/kernel/head.S | 3 +- > arch/riscv/mm/context.c | 2 +- > arch/riscv/mm/init.c | 194 ++++++++++++++++++++++++---- > arch/riscv/mm/ptdump.c | 49 +++++-- > 13 files changed, 412 insertions(+), 82 deletions(-) > Do you any remark regarding this patchset and the others ? Thanks, Alex
On Wed, 03 Jun 2020 01:10:56 PDT (-0700), alex@ghiti.fr wrote: > This patchset implements sv48 support at runtime. The kernel will try to > boot with 4-level page table and will fallback to 3-level if the HW does not > support it. > > The biggest advantage is that we only have one kernel for 64bit, which > is way easier to maintain. > > Folding the 4th level into a 3-level page table has almost no cost at > runtime. But as mentioned Palmer, the relocatable code generated is less > performant. > > At the moment, there is no way to build a 3-level page table non-relocatable > 64bit kernel. We agreed that distributions will use this runtime configuration > anyway, but Palmer proposed to introduce a new Kconfig, which I will do later > as sv48 support was asked for 5.8. > > Finally, the user can now ask for sv39 explicitly by using the device-tree > which will reduce memory footprint and reduce the number of memory accesses > in case of TLB miss. > > Changes in v2: > * Move variable declarations to pgtable.h in patch 5/7 as suggested by Anup > * Restore mmu-type properties in patch 6 as suggested by Anup > * Fix unused variable in patch 5 that was used in patch 6 > * Fix SPARSEMEM build (patch 2 was modified so I dropped the Reviewed-by) > * Applied various Reviewed-by > > Alexandre Ghiti (8): > riscv: Get rid of compile time logic with MAX_EARLY_MAPPING_SIZE > riscv: Allow to dynamically define VA_BITS > riscv: Simplify MAXPHYSMEM config > riscv: Prepare ptdump for vm layout dynamic addresses > riscv: Implement sv48 support > riscv: Allow user to downgrade to sv39 when hw supports sv48 > riscv: Use pgtable_l4_enabled to output mmu type in cpuinfo > riscv: Explicit comment about user virtual address space size > > arch/riscv/Kconfig | 34 ++--- > arch/riscv/include/asm/csr.h | 3 +- > arch/riscv/include/asm/fixmap.h | 1 + > arch/riscv/include/asm/page.h | 15 +++ > arch/riscv/include/asm/pgalloc.h | 36 ++++++ > arch/riscv/include/asm/pgtable-64.h | 97 +++++++++++++- > arch/riscv/include/asm/pgtable.h | 31 ++++- > arch/riscv/include/asm/sparsemem.h | 6 +- > arch/riscv/kernel/cpu.c | 23 ++-- > arch/riscv/kernel/head.S | 3 +- > arch/riscv/mm/context.c | 2 +- > arch/riscv/mm/init.c | 194 ++++++++++++++++++++++++---- > arch/riscv/mm/ptdump.c | 49 +++++-- > 13 files changed, 412 insertions(+), 82 deletions(-) Sorry I haven't had time to look at your patch sets for a bit, with the merge window everything got a bit busy. I'm collecting the rc1 fixes now, as we have some major issues, but with any luck I'll have time to start looking at larger stuff for for-next next week. Thanks!
This patchset implements sv48 support at runtime. The kernel will try to boot with 4-level page table and will fallback to 3-level if the HW does not support it. The biggest advantage is that we only have one kernel for 64bit, which is way easier to maintain. Folding the 4th level into a 3-level page table has almost no cost at runtime. But as mentioned Palmer, the relocatable code generated is less performant. At the moment, there is no way to build a 3-level page table non-relocatable 64bit kernel. We agreed that distributions will use this runtime configuration anyway, but Palmer proposed to introduce a new Kconfig, which I will do later as sv48 support was asked for 5.8. Finally, the user can now ask for sv39 explicitly by using the device-tree which will reduce memory footprint and reduce the number of memory accesses in case of TLB miss. Changes in v2: * Move variable declarations to pgtable.h in patch 5/7 as suggested by Anup * Restore mmu-type properties in patch 6 as suggested by Anup * Fix unused variable in patch 5 that was used in patch 6 * Fix SPARSEMEM build (patch 2 was modified so I dropped the Reviewed-by) * Applied various Reviewed-by Alexandre Ghiti (8): riscv: Get rid of compile time logic with MAX_EARLY_MAPPING_SIZE riscv: Allow to dynamically define VA_BITS riscv: Simplify MAXPHYSMEM config riscv: Prepare ptdump for vm layout dynamic addresses riscv: Implement sv48 support riscv: Allow user to downgrade to sv39 when hw supports sv48 riscv: Use pgtable_l4_enabled to output mmu type in cpuinfo riscv: Explicit comment about user virtual address space size arch/riscv/Kconfig | 34 ++--- arch/riscv/include/asm/csr.h | 3 +- arch/riscv/include/asm/fixmap.h | 1 + arch/riscv/include/asm/page.h | 15 +++ arch/riscv/include/asm/pgalloc.h | 36 ++++++ arch/riscv/include/asm/pgtable-64.h | 97 +++++++++++++- arch/riscv/include/asm/pgtable.h | 31 ++++- arch/riscv/include/asm/sparsemem.h | 6 +- arch/riscv/kernel/cpu.c | 23 ++-- arch/riscv/kernel/head.S | 3 +- arch/riscv/mm/context.c | 2 +- arch/riscv/mm/init.c | 194 ++++++++++++++++++++++++---- arch/riscv/mm/ptdump.c | 49 +++++-- 13 files changed, 412 insertions(+), 82 deletions(-)