| Message ID | 20220430153626.30660-1-palmer@rivosinc.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Generic Ticket Spinlocks | expand |
On Sat, Apr 30, 2022 at 5:36 PM Palmer Dabbelt <palmer@rivosinc.com> wrote: > > Comments on the v3 looked pretty straight-forward, essentially just that > RCsc issue I'd missed from the v2 and some cleanups. A part of the > discussion some additional possible cleanups came up related to the > qrwlock headers, but I hadn't looked at those yet and I had already > handled everything else. This went on the back burner, but given that > LoongArch appears to want to use it for their new port I think it's best > to just run with this and defer the other cleanups until later. > > I've placed the whole patch set at palmer/tspinlock-v4, and also tagged > the asm-generic bits as generic-ticket-spinlocks-v4. Ideally I'd like > to take that, along with the RISC-V patches, into my tree as there's > some RISC-V specific testing before things land in linux-next. This > passes all my testing, but I'll hold off until merging things anywhere > else to make sure everyone has time to look. There's no rush on my end > for this one, but I don't want to block LoongArch so I'll try to stay a > bit more on top of this one. I took another look as well and everything seems fine. I had expected that I would merge it into the asm-generic tree first and did not bother sending a separate Reviewed-by tag, but I agree that it's best if you create the branch. Can you add 'Reviewed-by: Arnd Bergmann <arnd@arndb.de>' to each patch and send me a pull request for a v5 tag so we can merge that into both the riscv and the asm-generic trees? Arnd
On Thu, 05 May 2022 04:09:46 PDT (-0700), Arnd Bergmann wrote: > On Sat, Apr 30, 2022 at 5:36 PM Palmer Dabbelt <palmer@rivosinc.com> wrote: >> >> Comments on the v3 looked pretty straight-forward, essentially just that >> RCsc issue I'd missed from the v2 and some cleanups. A part of the >> discussion some additional possible cleanups came up related to the >> qrwlock headers, but I hadn't looked at those yet and I had already >> handled everything else. This went on the back burner, but given that >> LoongArch appears to want to use it for their new port I think it's best >> to just run with this and defer the other cleanups until later. >> >> I've placed the whole patch set at palmer/tspinlock-v4, and also tagged >> the asm-generic bits as generic-ticket-spinlocks-v4. Ideally I'd like >> to take that, along with the RISC-V patches, into my tree as there's >> some RISC-V specific testing before things land in linux-next. This >> passes all my testing, but I'll hold off until merging things anywhere >> else to make sure everyone has time to look. There's no rush on my end >> for this one, but I don't want to block LoongArch so I'll try to stay a >> bit more on top of this one. > > I took another look as well and everything seems fine. I had expected > that I would merge it into the asm-generic tree first and did not bother > sending a separate Reviewed-by tag, but I agree that it's best if you > create the branch. > > Can you add 'Reviewed-by: Arnd Bergmann <arnd@arndb.de>' > to each patch and send me a pull request for a v5 tag so we can > merge that into both the riscv and the asm-generic trees? Yep. There were some other minor comments, I'll clean those up as well and send something soon.
Comments on the v3 looked pretty straight-forward, essentially just that RCsc issue I'd missed from the v2 and some cleanups. A part of the discussion some additional possible cleanups came up related to the qrwlock headers, but I hadn't looked at those yet and I had already handled everything else. This went on the back burner, but given that LoongArch appears to want to use it for their new port I think it's best to just run with this and defer the other cleanups until later. I've placed the whole patch set at palmer/tspinlock-v4, and also tagged the asm-generic bits as generic-ticket-spinlocks-v4. Ideally I'd like to take that, along with the RISC-V patches, into my tree as there's some RISC-V specific testing before things land in linux-next. This passes all my testing, but I'll hold off until merging things anywhere else to make sure everyone has time to look. There's no rush on my end for this one, but I don't want to block LoongArch so I'll try to stay a bit more on top of this one. Changes since v3 <20220414220214.24556-1-palmer@rivosinc.com>: * Added a smp_mb() in the lock slow-path, to make sure that is RCsc. * Fixed the header guards. Changes since v2 <20220319035457.2214979-1-guoren@kernel.org>: * Picked up Peter's SOBs, which were posted on the v1. * Re-ordered the first two patches, as they * Re-worded the RISC-V qrwlock patch, as it was a bit mushy. I also added a blurb in the qrwlock's top comment about this dependency. * Picked up Stafford's fix for big-endian systems, which I have not tested as I don't have one (at least easily availiable, I think the BE MIPS systems are still in that pile in my garage). * Call the generic version <asm-genenic/spinlock{_types}.h>, as there's really no utility to the version that only errors out. Changes since v1 <20220316232600.20419-1-palmer@rivosinc.com>: * Follow Arnd suggestion to make the patch series more generic. * Add csky in the series. * Combine RISC-V's two patches into one. * Modify openrisc's patch to suit the new generic version.