[v3,0/4] Introduce pmu-events support for HiFive Unmatched

Message

Nikita Shubin June 7, 2022, 1:16 p.m. UTC

From: Nikita Shubin <[e-mail]>

This series of patches introduces support for the RISC-V PMU identification and raw events matching between perf and the PMU.
The HiFive Unmatched board can now use all the counters with named events.

Unfortunately Mario is no longer interested in submitting this series, as there were no objections to v2 series, besides DT 
bindings which reside in U-Boot and shouldn't be exposed to Linux, i resending mostly original series with small sysfs pmu id fix.

See original cover letter by João Mário Domingos:
https://patchwork.kernel.org/project/linux-riscv/cover/[e-mail]/

Following addition was made to U-Boot device tree:
```
pmu {
	compatible = "riscv,pmu";
	riscv,event-to-mhpmcounters =
		<0x03 0x06 0x18
		0x10001 0x10002 0x18
		0x10009 0x10009 0x18
		0x10011 0x10011 0x18
		0x10019 0x10019 0x18
		0x10021 0x10021 0x18>;
	riscv,event-to-mhpmevent =
		<0x03 0x00000000 0x1801
		0x04 0x00000000 0x0302
		0x05 0x00000000 0x4000
		0x06 0x00000000 0x6001
		0x10001 0x00000000 0x0202
		0x10002 0x00000000 0x0402
		0x10009 0x00000000 0x0102
		0x10011 0x00000000 0x2002
		0x10019 0x00000000 0x1002
		0x10021 0x00000000 0x0802>;
	riscv,raw-event-to-mhpmcounters =
		<0x00000000 0x03ffff00 0x0 0x0 0x18
		0x00000000 0x0007ff01 0x0 0x1 0x18
		0x00000000 0x00003f02 0x0 0x2 0x18>;
};
```

Tested on the top of v5.19 which contains Atish Patra PMU series.

---
Changes in v3:
  - Change 'soc/soc:pmu/id' to 'riscv-pmu/id'
Changes in v2:
  - Fix compilation errors and warnings
  - Remove space idents
  - Correct formatting
---

João Mário Domingos (4):
  RISC-V: Create unique identification for SoC PMU
  RISC-V: Support CPUID for risc-v in perf
  RISC-V: Added generic pmu-events mapfile
  RISC-V: Added HiFive Unmatched PMU events

 arch/riscv/kernel/sbi.c                       |  3 +
 drivers/perf/riscv_pmu.c                      | 18 ++++
 drivers/perf/riscv_pmu_sbi.c                  | 47 ++++++++++
 tools/perf/arch/riscv/util/Build              |  1 +
 tools/perf/arch/riscv/util/header.c           | 66 +++++++++++++
 tools/perf/pmu-events/arch/riscv/mapfile.csv  | 15 +++
 .../pmu-events/arch/riscv/riscv-generic.json  | 20 ++++
 .../arch/riscv/sifive/u74/instructions.json   | 92 +++++++++++++++++++
 .../arch/riscv/sifive/u74/memory.json         | 32 +++++++
 .../arch/riscv/sifive/u74/microarch.json      | 57 ++++++++++++
 10 files changed, 351 insertions(+)
 create mode 100644 tools/perf/arch/riscv/util/header.c
 create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
 create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json