[v4,0/1] RISC-V: Create unique identification for SoC PMU

Message

Nikita Shubin June 19, 2022, 11:11 a.m. UTC

From: Nikita Shubin <[e-mail]>

Provide RISC-V SBI PMU id to distinguish different cores or SoCs via
"devices/platform/riscv-pmu/id" sysfs entry.

As per Will Deacon recomendation i am splitting the original series in parts,
first one is to provide a reasonable id for RISC-V SBI PMU. Events for Unmatched,
general RISCV and SBI Firmware bindings will be added later.

We can provide the PMU id as is marchid, mimpid, mvendorid as string, separated by a coma:

cat /sys/devices/platform/riscv-pmu/id 
0x70032,0x70032,0x0

In this case we are providing them as is as given by SBI extension.

Also i've added a string allocated on probe with pmuid, to avoid excess ecalls.

Atish would do you think about this ?

Sunil, thank you for reporting issue with 32-bit, i decided to make another approuch to problem.

Link: https://patchwork.kernel.org/project/linux-riscv/list/?series=648017
---
v3->v4:
- split series
- fix DEVICE_ATTR to use octal permissions
- use string for pmuid, instead of incoding some magical numbers
---
Nikita Shubin (1):
  RISC-V: Create unique identification for SoC PMU

 drivers/perf/riscv_pmu_sbi.c   | 41 ++++++++++++++++++++++++++++++++++
 include/linux/perf/riscv_pmu.h |  1 +
 2 files changed, 42 insertions(+)