| Message ID | 20220815120834.1562544-1-lewis.hanly@microchip.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Add Polarfire SoC GPIO support | expand |
On 2022-08-15 13:08, lewis.hanly@microchip.com wrote: > From: Lewis Hanly <lewis.hanly@microchip.com> > > > Add a driver to support the Polarfire SoC gpio controller. > Tested with latest 5.19 kernel. > > MPFS gpio interrupts are connected to IOMUX configured by system > register GPIO_INTERRUPT_FAB_CR(31:0). Interrupt connection for > some GPIO's to the PLIC (Platform Level Interrupt Controller) can be > shared (not directly connected) or direct if connection is available. > > previously upstreamed dt-bindings: gpio: microchip,mpfs-gpio.yaml > > Changes in v6 > Fixed typo causing compile issue with kernel 6.0-rc1 3 versions in just over 5 hours. How about taking a step back and *wait* for people to review this code? It isn't like this is going to be merged tomorrow anyway... The expected rate for new versions of a patch is about once a week (see Documentation/process/submitting-patches.rst). M.
From: Lewis Hanly <lewis.hanly@microchip.com> Add a driver to support the Polarfire SoC gpio controller. Tested with latest 5.19 kernel. MPFS gpio interrupts are connected to IOMUX configured by system register GPIO_INTERRUPT_FAB_CR(31:0). Interrupt connection for some GPIO's to the PLIC (Platform Level Interrupt Controller) can be shared (not directly connected) or direct if connection is available. previously upstreamed dt-bindings: gpio: microchip,mpfs-gpio.yaml Changes in v6 Fixed typo causing compile issue with kernel 6.0-rc1 Changes in v5 Added the const for the irqchip, removed in error from v2. Changes in v4 Changed the interrupt handling from Hierarchical flow to chained interrupt flow. The reason for the change was with hierarchical flow we requried a interrupt number mapping array to work with our HW and this was not acceptable. On reviewing the architecture the chained interrupt flow works better for our hardware and configurations which are not fixed in Silicon. Added support to read the optional DT property ngpios. Changes in v3: Changed order in kconfig. Removed blank lines in driver header/source file. Removed BYTE_BOUNDARY variable and use macro to do *4. mpfs_gpio_assign_bit parameter uses macro instead of (i * BYTE_BOUNDARY). Add correct definitions for direction. Change order of variables in mpfs_gpio_irq_set_type function. Return dev_err_probe instead of dev_err. Remove noise of dev_inf. Avoid using of_match_ptr. use devm_gpiochip_add_data(..) Update mpfs_gpio_remove. Changes in v2: Use raw_spinlock. Use __assign_bit() to assign bit, added a bool variable for value. Remove unnecessary checking gpio_index. Remove default from switch statement. Use const for irq_chip, name updated and use mask/unmask. Use latest kernel api irq set_chip. Implemented hierarchical interrupt chip support, although suggested to use chained interrupt flow I believe this fits better. Lewis Hanly (1): gpio: mpfs: add polarfire soc gpio support drivers/gpio/Kconfig | 7 + drivers/gpio/Makefile | 1 + drivers/gpio/gpio-mpfs.c | 317 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 325 insertions(+) create mode 100644 drivers/gpio/gpio-mpfs.c