[v3,0/3] perf: RISC-V: misc fixes and improvements

Message

Sergey Matyukevich Aug. 26, 2022, 8:34 p.m. UTC

Hi all,

It looks like the previous revision of these patches has slipped through
the cracks. So I am sending an updated version rebased on top of for-next
branch in riscv kernel tree.

Regards,
Sergey

v2 -> v3:

- rebased on top of for-next branch in riscv kernel tree
- added RB tag by Atish Patra to the first patch
- added perf throttle patch


Sergey Matyukevich (3):
  perf: RISC-V: fix access beyond allocated array
  perf: RISC-V: exclude invalid pmu counters from SBI calls
  perf: RISC-V: throttle perf events

 drivers/perf/riscv_pmu_legacy.c |  4 ++--
 drivers/perf/riscv_pmu_sbi.c    | 33 +++++++++++++++++++++------------
 include/linux/perf/riscv_pmu.h  |  2 +-
 3 files changed, 24 insertions(+), 15 deletions(-)