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[v2,0/3] RISC-V interrupt controller select cleanup

Message ID 20221118104300.85016-1-conor@kernel.org (mailing list archive)
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Series RISC-V interrupt controller select cleanup | expand

Message

Conor Dooley Nov. 18, 2022, 10:42 a.m. UTC
From: Conor Dooley <conor.dooley@microchip.com>

Hey Marc, Anup, Palmer,

Submitted a patch yesterday defaulting the SiFive PLIC driver to
enabled [0], and in the ensuing conversation Marc suggested just doing a
select at the arch level and dropping the user selectability completely.

Since we're already selecting SIFIVE_PLIC in Kconfig.socs for all of the
supported SoCs & selecting RISCV_INTC in the arch Kconfig itself,
patches 1 & 2 can go via the irqchip tree without any impact.

@Anup, by the same logic - I think we can also enable the AIA stuff via
selects at the arch level? Dumping as much from Kconfig.socs as possible
is the plan, so adding them there for SOC_VIRT kinda goes contrary to
that.

I spoke with Palmer today about putting my various bits of Kconfig.socs
cleanup on a branch, so I'll take patch 3. It's only in this series as
it is related work, rather due to any sort of dependency between the
patches.

Thanks,
Conor.

[0] https://lore.kernel.org/linux-riscv/86wn7tnx9a.wl-maz@kernel.org/

Conor Dooley (3):
  irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC
  irqchip/riscv-intc: remove user selectability of RISCV_INTC
  RISC-V: stop selecting SIFIVE_PLIC at the SoC level

 arch/riscv/Kconfig      |  1 +
 arch/riscv/Kconfig.socs |  5 -----
 drivers/irqchip/Kconfig | 21 ++-------------------
 3 files changed, 3 insertions(+), 24 deletions(-)

Comments

Marc Zyngier Nov. 26, 2022, 11:49 a.m. UTC | #1
On Fri, 18 Nov 2022 10:42:58 +0000,
Conor Dooley <conor@kernel.org> wrote:
> 
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Hey Marc, Anup, Palmer,
> 
> Submitted a patch yesterday defaulting the SiFive PLIC driver to
> enabled [0], and in the ensuing conversation Marc suggested just doing a
> select at the arch level and dropping the user selectability completely.
> 
> Since we're already selecting SIFIVE_PLIC in Kconfig.socs for all of the
> supported SoCs & selecting RISCV_INTC in the arch Kconfig itself,
> patches 1 & 2 can go via the irqchip tree without any impact.
> 
> @Anup, by the same logic - I think we can also enable the AIA stuff via
> selects at the arch level? Dumping as much from Kconfig.socs as possible
> is the plan, so adding them there for SOC_VIRT kinda goes contrary to
> that.
> 
> I spoke with Palmer today about putting my various bits of Kconfig.socs
> cleanup on a branch, so I'll take patch 3. It's only in this series as
> it is related work, rather due to any sort of dependency between the
> patches.
> 
> Thanks,
> Conor.
> 
> [0] https://lore.kernel.org/linux-riscv/86wn7tnx9a.wl-maz@kernel.org/
> 
> Conor Dooley (3):
>   irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC
>   irqchip/riscv-intc: remove user selectability of RISCV_INTC
>   RISC-V: stop selecting SIFIVE_PLIC at the SoC level
> 
>  arch/riscv/Kconfig      |  1 +
>  arch/riscv/Kconfig.socs |  5 -----
>  drivers/irqchip/Kconfig | 21 ++-------------------
>  3 files changed, 3 insertions(+), 24 deletions(-)

For the series:

Acked-by: Marc Zyngier <maz@kernel.org>

Please take the whole thing via the RISC-V tree.

Thanks,

	M.
Palmer Dabbelt Dec. 8, 2022, 11:58 p.m. UTC | #2
On Fri, 18 Nov 2022 10:42:58 +0000, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Hey Marc, Anup, Palmer,
> 
> Submitted a patch yesterday defaulting the SiFive PLIC driver to
> enabled [0], and in the ensuing conversation Marc suggested just doing a
> select at the arch level and dropping the user selectability completely.
> 
> [...]

Applied, thanks!

[1/3] irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC
      https://git.kernel.org/palmer/c/fdb1742aff43
[2/3] irqchip/riscv-intc: remove user selectability of RISCV_INTC
      https://git.kernel.org/palmer/c/d8fb13070c3c
[3/3] RISC-V: stop selecting SIFIVE_PLIC at the SoC level
      https://git.kernel.org/palmer/c/bf3d7b1d8499

Best regards,
patchwork-bot+linux-riscv@kernel.org Dec. 9, 2022, 1:30 a.m. UTC | #3
Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Fri, 18 Nov 2022 10:42:58 +0000 you wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Hey Marc, Anup, Palmer,
> 
> Submitted a patch yesterday defaulting the SiFive PLIC driver to
> enabled [0], and in the ensuing conversation Marc suggested just doing a
> select at the arch level and dropping the user selectability completely.
> 
> [...]

Here is the summary with links:
  - [v2,1/3] irqchip/sifive-plic: remove user selectability of SIFIVE_PLIC
    https://git.kernel.org/riscv/c/fdb1742aff43
  - [v2,2/3] irqchip/riscv-intc: remove user selectability of RISCV_INTC
    https://git.kernel.org/riscv/c/d8fb13070c3c
  - [v2,3/3] RISC-V: stop selecting SIFIVE_PLIC at the SoC level
    https://git.kernel.org/riscv/c/bf3d7b1d8499

You are awesome, thank you!