[v2,0/7] PolarFire SoC Auto Update Support

Message

Conor Dooley March 31, 2023, 7:18 a.m. UTC

Hey all,

This patchset adds support for the "Auto Update" feature on PolarFire
SoC that allows for writing an FPGA bistream to the SPI flash connected
to the system controller.
On powercycle (or reboot depending on how the firmware implements the
openSBI SRST extension) "Auto Update" will take place, and program the
FPGA with the contents of the SPI flash - provided that that image is
valid and an actual upgrade from that already programmed!

Unfortunately, this series is not really testable yet - the Engineering
Sample silicon on most dev boards has a bug in the QSPI controller
connected to the system controller's flash and cannot access it.
Pre-production and later silicon has this bug fixed.

I previously posted an RFC about my approach in this driver, since as a
flash-based FPGA we are somewhat different to the existing
self-reprogramming drivers here. That RFC is here:
https://lore.kernel.org/linux-fpga/[e-mail]/

This series depends on the following fixes:
https://lore.kernel.org/all/d7c3ec51-8493-444a-bdec-2a30b0a15bdc@spud/

The patch adding the driver depends on the soc patches earlier in the
series, so taking both through the same tree makes sense. Depending on
sequencing with the dependencies, me taking it through the soc tree
(with Acks etc of course) may make the most sense.

Cheers,
Conor.

Changes in v2:
- per Russ' suggestion, the driver has been switched to using the
  firmware-upload API rather than the fpga one
- as a result of that change, the structure of the driver has changed
  significantly, although most of that is reshuffling existing code
  around
- check if the upgrade is possible in probe and fail if it isn't
- only write the image index if it is not already set
- delete the now unneeded debugfs bits

CC: Conor Dooley <[e-mail]>
CC: Daire McNamara <[e-mail]>
CC: Rob Herring <[e-mail]>
CC: Krzysztof Kozlowski <[e-mail]>
CC: Moritz Fischer <[e-mail]>
CC: Wu Hao <[e-mail]>
CC: Xu Yilun <[e-mail]>
CC: Tom Rix <[e-mail]>
CC; Russ Weight <[e-mail]>
CC: [e-mail]
CC: [e-mail]
CC: [e-mail]
CC: [e-mail]

Conor Dooley (7):
  soc: microchip: mpfs: add a prefix to rx_callback()
  dt-bindings: soc: microchip: add a property for system controller
    flash
  soc: microchip: mpfs: enable access to the system controller's flash
  soc: microchip: mpfs: print service status in warning message
  soc: microchip: mpfs: add auto-update subdev to system controller
  fpga: add PolarFire SoC Auto Update support
  riscv: dts: microchip: add the mpfs' system controller qspi &
    associated flash

 .../microchip,mpfs-sys-controller.yaml        |  10 +
 .../boot/dts/microchip/mpfs-icicle-kit.dts    |  21 +
 arch/riscv/boot/dts/microchip/mpfs.dtsi       |  24 +-
 drivers/fpga/Kconfig                          |  11 +
 drivers/fpga/Makefile                         |   3 +-
 drivers/fpga/microchip-auto-update.c          | 494 ++++++++++++++++++
 drivers/soc/microchip/Kconfig                 |   1 +
 drivers/soc/microchip/mpfs-sys-controller.c   |  37 +-
 include/soc/microchip/mpfs.h                  |   2 +
 9 files changed, 591 insertions(+), 12 deletions(-)
 create mode 100644 drivers/fpga/microchip-auto-update.c

Comments

Xu Yilun April 2, 2023, 8 a.m. UTC | #1

On 2023-03-31 at 08:18:16 +0100, Conor Dooley wrote:
> Hey all,
> 
> This patchset adds support for the "Auto Update" feature on PolarFire
> SoC that allows for writing an FPGA bistream to the SPI flash connected
> to the system controller.
> On powercycle (or reboot depending on how the firmware implements the
> openSBI SRST extension) "Auto Update" will take place, and program the
> FPGA with the contents of the SPI flash - provided that that image is
> valid and an actual upgrade from that already programmed!
> 
> Unfortunately, this series is not really testable yet - the Engineering
> Sample silicon on most dev boards has a bug in the QSPI controller
> connected to the system controller's flash and cannot access it.
> Pre-production and later silicon has this bug fixed.
> 
> I previously posted an RFC about my approach in this driver, since as a
> flash-based FPGA we are somewhat different to the existing
> self-reprogramming drivers here. That RFC is here:
> https://lore.kernel.org/linux-fpga/[e-mail]/
> 
> This series depends on the following fixes:
> https://lore.kernel.org/all/d7c3ec51-8493-444a-bdec-2a30b0a15bdc@spud/

Is that series already merged? If yes, just remove this line.
If no, either put all of them in one series, or still make this series
as RFC until the dependency is resolved.

Thanks,
Yilun

> 
> The patch adding the driver depends on the soc patches earlier in the
> series, so taking both through the same tree makes sense. Depending on
> sequencing with the dependencies, me taking it through the soc tree
> (with Acks etc of course) may make the most sense.
> 
> Cheers,
> Conor.
> 
> Changes in v2:
> - per Russ' suggestion, the driver has been switched to using the
>   firmware-upload API rather than the fpga one
> - as a result of that change, the structure of the driver has changed
>   significantly, although most of that is reshuffling existing code
>   around
> - check if the upgrade is possible in probe and fail if it isn't
> - only write the image index if it is not already set
> - delete the now unneeded debugfs bits
> 
> CC: Conor Dooley <[e-mail]>
> CC: Daire McNamara <[e-mail]>
> CC: Rob Herring <[e-mail]>
> CC: Krzysztof Kozlowski <[e-mail]>
> CC: Moritz Fischer <[e-mail]>
> CC: Wu Hao <[e-mail]>
> CC: Xu Yilun <[e-mail]>
> CC: Tom Rix <[e-mail]>
> CC; Russ Weight <[e-mail]>
> CC: [e-mail]
> CC: [e-mail]
> CC: [e-mail]
> CC: [e-mail]
> 
> Conor Dooley (7):
>   soc: microchip: mpfs: add a prefix to rx_callback()
>   dt-bindings: soc: microchip: add a property for system controller
>     flash
>   soc: microchip: mpfs: enable access to the system controller's flash
>   soc: microchip: mpfs: print service status in warning message
>   soc: microchip: mpfs: add auto-update subdev to system controller
>   fpga: add PolarFire SoC Auto Update support
>   riscv: dts: microchip: add the mpfs' system controller qspi &
>     associated flash
> 
>  .../microchip,mpfs-sys-controller.yaml        |  10 +
>  .../boot/dts/microchip/mpfs-icicle-kit.dts    |  21 +
>  arch/riscv/boot/dts/microchip/mpfs.dtsi       |  24 +-
>  drivers/fpga/Kconfig                          |  11 +
>  drivers/fpga/Makefile                         |   3 +-
>  drivers/fpga/microchip-auto-update.c          | 494 ++++++++++++++++++
>  drivers/soc/microchip/Kconfig                 |   1 +
>  drivers/soc/microchip/mpfs-sys-controller.c   |  37 +-
>  include/soc/microchip/mpfs.h                  |   2 +
>  9 files changed, 591 insertions(+), 12 deletions(-)
>  create mode 100644 drivers/fpga/microchip-auto-update.c
> 
> -- 
> 2.39.2
>

Conor Dooley April 2, 2023, 8:23 a.m. UTC | #2

On 2 April 2023 09:00:34 IST, Xu Yilun <[e-mail]> wrote:
>On 2023-03-31 at 08:18:16 +0100, Conor Dooley wrote:
>> Hey all,
>> 
>> This patchset adds support for the "Auto Update" feature on PolarFire
>> SoC that allows for writing an FPGA bistream to the SPI flash connected
>> to the system controller.
>> On powercycle (or reboot depending on how the firmware implements the
>> openSBI SRST extension) "Auto Update" will take place, and program the
>> FPGA with the contents of the SPI flash - provided that that image is
>> valid and an actual upgrade from that already programmed!
>> 
>> Unfortunately, this series is not really testable yet - the Engineering
>> Sample silicon on most dev boards has a bug in the QSPI controller
>> connected to the system controller's flash and cannot access it.
>> Pre-production and later silicon has this bug fixed.
>> 
>> I previously posted an RFC about my approach in this driver, since as a
>> flash-based FPGA we are somewhat different to the existing
>> self-reprogramming drivers here. That RFC is here:
>> https://lore.kernel.org/linux-fpga/[e-mail]/
>> 
>> This series depends on the following fixes:
>> https://lore.kernel.org/all/d7c3ec51-8493-444a-bdec-2a30b0a15bdc@spud/
>
>Is that series already merged? If yes, just remove this line.
>If no, either put all of them in one series, or still make this series
>as RFC until the dependency is resolved.

Merged into what?
I'll be applying the dependencies tomorrow probably.

>
>Thanks,
>Yilun
>
>> 
>> The patch adding the driver depends on the soc patches earlier in the
>> series, so taking both through the same tree makes sense. Depending on
>> sequencing with the dependencies, me taking it through the soc tree
>> (with Acks etc of course) may make the most sense.
>> 
>> Cheers,
>> Conor.
>> 
>> Changes in v2:
>> - per Russ' suggestion, the driver has been switched to using the
>>   firmware-upload API rather than the fpga one
>> - as a result of that change, the structure of the driver has changed
>>   significantly, although most of that is reshuffling existing code
>>   around
>> - check if the upgrade is possible in probe and fail if it isn't
>> - only write the image index if it is not already set
>> - delete the now unneeded debugfs bits
>> 
>> CC: Conor Dooley <[e-mail]>
>> CC: Daire McNamara <[e-mail]>
>> CC: Rob Herring <[e-mail]>
>> CC: Krzysztof Kozlowski <[e-mail]>
>> CC: Moritz Fischer <[e-mail]>
>> CC: Wu Hao <[e-mail]>
>> CC: Xu Yilun <[e-mail]>
>> CC: Tom Rix <[e-mail]>
>> CC; Russ Weight <[e-mail]>
>> CC: [e-mail]
>> CC: [e-mail]
>> CC: [e-mail]
>> CC: [e-mail]
>> 
>> Conor Dooley (7):
>>   soc: microchip: mpfs: add a prefix to rx_callback()
>>   dt-bindings: soc: microchip: add a property for system controller
>>     flash
>>   soc: microchip: mpfs: enable access to the system controller's flash
>>   soc: microchip: mpfs: print service status in warning message
>>   soc: microchip: mpfs: add auto-update subdev to system controller
>>   fpga: add PolarFire SoC Auto Update support
>>   riscv: dts: microchip: add the mpfs' system controller qspi &
>>     associated flash
>> 
>>  .../microchip,mpfs-sys-controller.yaml        |  10 +
>>  .../boot/dts/microchip/mpfs-icicle-kit.dts    |  21 +
>>  arch/riscv/boot/dts/microchip/mpfs.dtsi       |  24 +-
>>  drivers/fpga/Kconfig                          |  11 +
>>  drivers/fpga/Makefile                         |   3 +-
>>  drivers/fpga/microchip-auto-update.c          | 494 ++++++++++++++++++
>>  drivers/soc/microchip/Kconfig                 |   1 +
>>  drivers/soc/microchip/mpfs-sys-controller.c   |  37 +-
>>  include/soc/microchip/mpfs.h                  |   2 +
>>  9 files changed, 591 insertions(+), 12 deletions(-)
>>  create mode 100644 drivers/fpga/microchip-auto-update.c
>> 
>> -- 
>> 2.39.2
>>

Conor Dooley April 3, 2023, 7:34 p.m. UTC | #3

From: Conor Dooley <[e-mail]>

On Fri, 31 Mar 2023 08:18:16 +0100, Conor Dooley wrote:
> Hey all,
> 
> This patchset adds support for the "Auto Update" feature on PolarFire
> SoC that allows for writing an FPGA bistream to the SPI flash connected
> to the system controller.
> On powercycle (or reboot depending on how the firmware implements the
> openSBI SRST extension) "Auto Update" will take place, and program the
> FPGA with the contents of the SPI flash - provided that that image is
> valid and an actual upgrade from that already programmed!
> 
> [...]

Gonna take this one patch, since it's got ~nothing to do with the rest
of the series really, so:

Applied to riscv-soc-for-next, thanks!

[1/7] soc: microchip: mpfs: add a prefix to rx_callback()
      https://git.kernel.org/conor/c/4dd472bdafcb

Thanks,
Conor.