[v1,0/7] ISA string parser cleanups++

Message

Conor Dooley May 4, 2023, 6:14 p.m. UTC

From: Conor Dooley <[e-mail]>

This stuff goes on top of riscv/for-next plus this series from Yangyu
that made me go looking at the ISA string parser again:
https://lore.kernel.org/all/[e-mail]/

With that out of the way, here are some cleanups for our riscv,isa
handling.
One of these patches is yoinked from Sunil's ACPI series & tweaked
slightly since this needs to apply independently of that, that runs the
isa string parsing loop only over _possible_ cpus.

Other than that, there are some bits that were discussed with Drew on
the "should we allow caps" threads that I have now created patches for:
- splitting of riscv_of_processor_hartid() into two distinct functions,
  one for use purely during early boot, prior to the establishment of
  the possible-cpus mask & another to fit the other current use-cases.
- this allows us to then completely skip some validation of the hartid
  in the parser.
- the biggest diff in the series is a rework of the comments in the
  parser, as I have mostly found the existing (sparse) ones to not be
  all that helpful whenever I have to go back and look at it.
- from writing the comments, I found a conditional doing a bit of a
  dance that I found counter-intuitive, so I've had a go at making that
  match what I would expect a little better.
- `i` implies `Zicsr` & `Zifence`, so add them as extensions and set
  them for the craic. Sure why not like. Of all the patches here, this
  is the one I can most take-or-leave.

Cheers,
Conor.

CC: Paul Walmsley <[e-mail]>
CC: Palmer Dabbelt <[e-mail]>
CC: Conor Dooley <[e-mail]>
CC: Andrew Jones <[e-mail]>
CC: Sunil V L <[e-mail]>
CC: Yangyu Chen <[e-mail]>
CC: [e-mail]

Conor Dooley (6):
  RISC-V: simplify register width check in ISA string parsing
  RISC-V: split early & late of_node to hartid mapping
  RISC-V: validate riscv,isa at boot, not during ISA string parsing
  RISC-V: rework comments in ISA string parser
  RISC-V: remove decrement/increment dance in ISA string parser
  RISC-V: always report presence of Zicsr/Zifencei

Sunil V L (1):
  RISC-V: only iterate over possible CPUs in ISA string parser

 arch/riscv/include/asm/hwcap.h     |   2 +
 arch/riscv/include/asm/processor.h |   1 +
 arch/riscv/kernel/cpu.c            |  32 +++++++-
 arch/riscv/kernel/cpufeature.c     | 114 ++++++++++++++++++++++-------
 arch/riscv/kernel/smpboot.c        |   2 +-
 5 files changed, 118 insertions(+), 33 deletions(-)


base-commit: c2d3c8441e3ddbfe41fea9282ddc6ee372e154cd
prerequisite-patch-id: 50cc6c119a7f8f60b06829b2fafc90c9817f532c
prerequisite-patch-id: 4e2f66d8590db938d2e1a4e9bfaad58ee0ab3525