| Message ID | 20230710131902.1459180-1-apatel@ventanamicro.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Misc RISC-V timer driver improvements | expand |
On Mon, Jul 10, 2023 at 06:49:00PM +0530, Anup Patel wrote: > This series does two improvements to the RISC-V timer driver: > 1) Keep timer interrupt enable state in-sync with interrupt subsystem > 2) Increase rating of clock event device when Sstc is available > > These patches can also be found in the riscv_timer_imp_v1 branch at: > https://github.com/avpatel/linux.git Other than wondering why you opted for 450 (curiosity really), this stuff looks fine to me. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor.
On Tue, Jul 11, 2023 at 4:51 PM Conor Dooley <conor.dooley@microchip.com> wrote: > > On Mon, Jul 10, 2023 at 06:49:00PM +0530, Anup Patel wrote: > > This series does two improvements to the RISC-V timer driver: > > 1) Keep timer interrupt enable state in-sync with interrupt subsystem > > 2) Increase rating of clock event device when Sstc is available > > > > These patches can also be found in the riscv_timer_imp_v1 branch at: > > https://github.com/avpatel/linux.git > > Other than wondering why you opted for 450 (curiosity really), this > stuff looks fine to me. It is the same as the rating for clock_event_device used by ARM arch timer. (Refer, __arch_timer_setup() in drivers/clocksource/arm_arch_timer.c) > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Cheers, > Conor. Regards, Anup
On Tue, Jul 11, 2023 at 05:07:11PM +0530, Anup Patel wrote: > On Tue, Jul 11, 2023 at 4:51 PM Conor Dooley <conor.dooley@microchip.com> wrote: > > Other than wondering why you opted for 450 (curiosity really), this > > stuff looks fine to me. > > It is the same as the rating for clock_event_device used by ARM arch timer. That's what I figured, thanks!
On Mon, 10 Jul 2023 06:19:00 PDT (-0700), apatel@ventanamicro.com wrote: > This series does two improvements to the RISC-V timer driver: > 1) Keep timer interrupt enable state in-sync with interrupt subsystem > 2) Increase rating of clock event device when Sstc is available > > These patches can also be found in the riscv_timer_imp_v1 branch at: > https://github.com/avpatel/linux.git > > Anup Patel (2): > clocksource: timer-riscv: Don't enable/disable timer interrupt > clocksource: timer-riscv: Increase rating of clock_event_device for > Sstc > > drivers/clocksource/timer-riscv.c | 17 +++++++++++++++-- > 1 file changed, 15 insertions(+), 2 deletions(-) Acked-by: Palmer Dabbelt <palmer@rivosinc.com> in case the clock folks want to pick these up. Otherwise I'll look more closely and take them via the RISC-V tree. Thanks!
This series does two improvements to the RISC-V timer driver: 1) Keep timer interrupt enable state in-sync with interrupt subsystem 2) Increase rating of clock event device when Sstc is available These patches can also be found in the riscv_timer_imp_v1 branch at: https://github.com/avpatel/linux.git Anup Patel (2): clocksource: timer-riscv: Don't enable/disable timer interrupt clocksource: timer-riscv: Increase rating of clock_event_device for Sstc drivers/clocksource/timer-riscv.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-)