| Message ID | 20230713-target-much-8ac624e90df8@wendy (mailing list archive) |
|---|---|
| Headers | show |
| Series | RISC-V: Probe DT extension support using riscv,isa-extensions & riscv,isa-base | expand |
Hello: This series was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Thu, 13 Jul 2023 13:10:58 +0100 you wrote: > Hey, > > Based on my latest iteration of deprecating riscv,isa [1], here's an > implementation of the new properties for Linux. The first few patches, > up to "RISC-V: split riscv_fill_hwcap() in 3", are all prep work that > further tames some of the extension related code, on top of my already > applied series that cleans up the ISA string parser. > Perhaps "RISC-V: shunt isa_ext_arr to cpufeature.c" is a bit gratuitous, > but I figured a bit of coalescing of extension related data structures > would be a good idea. Note that riscv,isa will still be used in the > absence of the new properties. Palmer suggested adding a Kconfig option > to turn off the fallback for DT, which I have gone and done. It's locked > behind the NONPORTABLE option for good reason. > > [...] Here is the summary with links: - [v5,01/11] RISC-V: Provide a more helpful error message on invalid ISA strings https://git.kernel.org/riscv/c/230598939678 - [v5,02/11] RISC-V: don't parse dt/acpi isa string to get rv32/rv64 https://git.kernel.org/riscv/c/67270fb388fe - [v5,03/11] RISC-V: drop a needless check in print_isa_ext() https://git.kernel.org/riscv/c/131033689da2 - [v5,04/11] RISC-V: shunt isa_ext_arr to cpufeature.c https://git.kernel.org/riscv/c/8135ade32c0d - [v5,05/11] RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() https://git.kernel.org/riscv/c/37f988dcec05 - [v5,06/11] RISC-V: add missing single letter extension definitions https://git.kernel.org/riscv/c/c30556e318cc - [v5,07/11] RISC-V: add single letter extensions to riscv_isa_ext https://git.kernel.org/riscv/c/effc122ad176 - [v5,08/11] RISC-V: split riscv_fill_hwcap() in 3 https://git.kernel.org/riscv/c/4265b0ec5ee7 - [v5,09/11] RISC-V: enable extension detection from dedicated properties https://git.kernel.org/riscv/c/90700a4fbfaf - [v5,10/11] RISC-V: try new extension properties in of_early_processor_hartid() https://git.kernel.org/riscv/c/c98f136aedbd - [v5,11/11] RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa" https://git.kernel.org/riscv/c/496ea826d1e1 You are awesome, thank you!
Hey, Based on my latest iteration of deprecating riscv,isa [1], here's an implementation of the new properties for Linux. The first few patches, up to "RISC-V: split riscv_fill_hwcap() in 3", are all prep work that further tames some of the extension related code, on top of my already applied series that cleans up the ISA string parser. Perhaps "RISC-V: shunt isa_ext_arr to cpufeature.c" is a bit gratuitous, but I figured a bit of coalescing of extension related data structures would be a good idea. Note that riscv,isa will still be used in the absence of the new properties. Palmer suggested adding a Kconfig option to turn off the fallback for DT, which I have gone and done. It's locked behind the NONPORTABLE option for good reason. In v2, I've also come up with a more reasonable name for the new function I added & fixed up various comments from Drew and Evan. In v3, there's the new commandline option that Drew suggested. I have Also picked up a patch from Palmer that adds more helpful prints where harts fail the checks in riscv_early_of_processor_id(), and I've sprinkled a few more of those prints in my new additions to the function. v4 just rebases on v6.5-rc1 and fixes the nommu build issue due to a missing __init. In v5, I've fixed issues spotted by myself & Evan. I'm not the worlds biggest fan of the strlen() calls inside the macro - but that's going to go away again almost immediately if the scalar crypto stuff gets merged. I also spotted an issue with a rebase I did at some point, where the dedicated properties did not use isainfo->isa & created a bitmap for each cpu, which would've caused the per-hart extension tracking to break. Cheers, Conor. [1] (it's in v6.5-rc1 now) CC: Rob Herring <robh+dt@kernel.org> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> CC: Paul Walmsley <paul.walmsley@sifive.com> CC: Palmer Dabbelt <palmer@dabbelt.com> CC: Albert Ou <aou@eecs.berkeley.edu> CC: Jonathan Corbet <corbet@lwn.net> CC: Andrew Jones <ajones@ventanamicro.com> CC: Heiko Stuebner <heiko.stuebner@vrull.eu> CC: Evan Green <evan@rivosinc.com> CC: Sunil V L <sunilvl@ventanamicro.com> CC: linux-doc@vger.kernel.org CC: linux-riscv@lists.infradead.org CC: devicetree@vger.kernel.org CC: linux-kernel@vger.kernel.org Conor Dooley (9): RISC-V: drop a needless check in print_isa_ext() RISC-V: shunt isa_ext_arr to cpufeature.c RISC-V: repurpose riscv_isa_ext array in riscv_fill_hwcap() RISC-V: add missing single letter extension definitions RISC-V: add single letter extensions to riscv_isa_ext RISC-V: split riscv_fill_hwcap() in 3 RISC-V: enable extension detection from dedicated properties RISC-V: try new extension properties in of_early_processor_hartid() RISC-V: provide Kconfig & commandline options to control parsing "riscv,isa" Heiko Stuebner (1): RISC-V: don't parse dt/acpi isa string to get rv32/rv64 Palmer Dabbelt (1): RISC-V: Provide a more helpful error message on invalid ISA strings .../admin-guide/kernel-parameters.txt | 7 + arch/riscv/Kconfig | 18 + arch/riscv/include/asm/hwcap.h | 17 +- arch/riscv/kernel/cpu.c | 179 +++--- arch/riscv/kernel/cpufeature.c | 521 ++++++++++++------ 5 files changed, 439 insertions(+), 303 deletions(-)