[v3,0/4] riscv: tlb flush improvements

Message

Alexandre Ghiti Aug. 1, 2023, 8:53 a.m. UTC

This series optimizes the tlb flushes on riscv which used to simply
flush the whole tlb whatever the size of the range to flush or the size
of the stride.

Patch 3 introduces a threshold that is microarchitecture specific and
will very likely be modified by vendors, not sure though which mechanism
we'll use to do that (dt? alternatives? vendor initialization code?).

Next steps would be to implement:
- svinval extension as Mayuresh did here [1]
- BATCHED_UNMAP_TLB_FLUSH (I'll wait for arm64 patchset to land)
- MMU_GATHER_RCU_TABLE_FREE
- MMU_GATHER_MERGE_VMAS

Any other idea welcome.

[1] https://lore.kernel.org/linux-riscv/[e-mail]/

Changes in v3:
- Add RB from Andrew, thanks!
- Unwrap a few lines, as suggested by Andrew
- Introduce defines for -1 constants used in tlbflush.c, as suggested by Andrew and Conor
- Use huge_page_size() directly instead of using the shift, as suggested by Andrew
- Remove misleading comments as suggested by Conor

Changes in v2:
- Make static tlb_flush_all_threshold, we'll figure out later how to
  override this value on a vendor basis, as suggested by Conor and Palmer
- Fix nommu build, as reported by Conor

Alexandre Ghiti (4):
  riscv: Improve flush_tlb()
  riscv: Improve flush_tlb_range() for hugetlb pages
  riscv: Make __flush_tlb_range() loop over pte instead of flushing the
    whole tlb
  riscv: Improve flush_tlb_kernel_range()

 arch/riscv/include/asm/tlb.h      |  8 ++-
 arch/riscv/include/asm/tlbflush.h | 12 ++--
 arch/riscv/mm/tlbflush.c          | 98 ++++++++++++++++++++++++++-----
 3 files changed, 99 insertions(+), 19 deletions(-)

Comments

[e-mail] Sept. 6, 2023, 1 p.m. UTC | #1

Hello:

This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <[e-mail]>:

On Tue,  1 Aug 2023 10:53:58 +0200 you wrote:
> This series optimizes the tlb flushes on riscv which used to simply
> flush the whole tlb whatever the size of the range to flush or the size
> of the stride.
> 
> Patch 3 introduces a threshold that is microarchitecture specific and
> will very likely be modified by vendors, not sure though which mechanism
> we'll use to do that (dt? alternatives? vendor initialization code?).
> 
> [...]

Here is the summary with links:
  - [v3,1/4] riscv: Improve flush_tlb()
    https://git.kernel.org/riscv/c/1245a70831b9
  - [v3,2/4] riscv: Improve flush_tlb_range() for hugetlb pages
    https://git.kernel.org/riscv/c/9d6fb1015281
  - [v3,3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb
    https://git.kernel.org/riscv/c/cfe5187b7e93
  - [v3,4/4] riscv: Improve flush_tlb_kernel_range()
    https://git.kernel.org/riscv/c/bbc9ad35b51b

You are awesome, thank you!

Samuel Holland Sept. 9, 2023, 8:11 p.m. UTC | #2

On 8/1/23 03:53, Alexandre Ghiti wrote:
> This series optimizes the tlb flushes on riscv which used to simply
> flush the whole tlb whatever the size of the range to flush or the size
> of the stride.
> 
> Patch 3 introduces a threshold that is microarchitecture specific and
> will very likely be modified by vendors, not sure though which mechanism
> we'll use to do that (dt? alternatives? vendor initialization code?).

Certainly we would want to set the threshold to zero on SiFive platforms
affected by CIP-1200, since they cannot use address-based sfence.vma at
all. At least this case could be handled in the existing errata patch
function. I don't know about other platforms.

Regards,
Samuel

> 
> Next steps would be to implement:
> - svinval extension as Mayuresh did here [1]
> - BATCHED_UNMAP_TLB_FLUSH (I'll wait for arm64 patchset to land)
> - MMU_GATHER_RCU_TABLE_FREE
> - MMU_GATHER_MERGE_VMAS
> 
> Any other idea welcome.
> 
> [1] https://lore.kernel.org/linux-riscv/[e-mail]/
> 
> Changes in v3:
> - Add RB from Andrew, thanks!
> - Unwrap a few lines, as suggested by Andrew
> - Introduce defines for -1 constants used in tlbflush.c, as suggested by Andrew and Conor
> - Use huge_page_size() directly instead of using the shift, as suggested by Andrew
> - Remove misleading comments as suggested by Conor
> 
> Changes in v2:
> - Make static tlb_flush_all_threshold, we'll figure out later how to
>   override this value on a vendor basis, as suggested by Conor and Palmer
> - Fix nommu build, as reported by Conor
> 
> Alexandre Ghiti (4):
>   riscv: Improve flush_tlb()
>   riscv: Improve flush_tlb_range() for hugetlb pages
>   riscv: Make __flush_tlb_range() loop over pte instead of flushing the
>     whole tlb
>   riscv: Improve flush_tlb_kernel_range()
> 
>  arch/riscv/include/asm/tlb.h      |  8 ++-
>  arch/riscv/include/asm/tlbflush.h | 12 ++--
>  arch/riscv/mm/tlbflush.c          | 98 ++++++++++++++++++++++++++-----
>  3 files changed, 99 insertions(+), 19 deletions(-)
>