| Message ID | 20231003035226.1945725-1-apatel@ventanamicro.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | KVM RISC-V Conditional Operations | expand |
On Tue, Oct 3, 2023 at 9:22 AM Anup Patel <apatel@ventanamicro.com> wrote: > > This series extends KVM RISC-V to allow Guest/VM discover and use > conditional operations related ISA extensions (namely XVentanaCondOps > and Zicond). > > To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1 > branch at: https://github.com/avpatel/kvmtool.git > > These patches are based upon the latest riscv_kvm_queue and can also be > found in the riscv_kvm_condops_v3 branch at: > https://github.com/avpatel/linux.git > > Changes since v2: > - Dropped patch1, patch2, and patch5 since these patches don't meet > the requirements of patch acceptance policy. > > Changes since v1: > - Rebased the series on riscv_kvm_queue > - Split PATCH1 and PATCH2 of v1 series into two patches > - Added separate test configs for XVentanaCondOps and Zicond in PATCH7 > of v1 series. > > Anup Patel (6): > dt-bindings: riscv: Add Zicond extension entry > RISC-V: Detect Zicond from ISA string > RISC-V: KVM: Allow Zicond extension for Guest/VM > KVM: riscv: selftests: Add senvcfg register to get-reg-list test > KVM: riscv: selftests: Add smstateen registers to get-reg-list test > KVM: riscv: selftests: Add condops extensions to get-reg-list test Queued this series for Linux-6.7 Thanks, Anup > > .../devicetree/bindings/riscv/extensions.yaml | 6 +++ > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/include/uapi/asm/kvm.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > arch/riscv/kvm/vcpu_onereg.c | 2 + > .../selftests/kvm/riscv/get-reg-list.c | 54 +++++++++++++++++++ > 6 files changed, 65 insertions(+) > > -- > 2.34.1 >
Hi Palmer, On Thu, Oct 5, 2023 at 11:35 AM Anup Patel <anup@brainfault.org> wrote: > > On Tue, Oct 3, 2023 at 9:22 AM Anup Patel <apatel@ventanamicro.com> wrote: > > > > This series extends KVM RISC-V to allow Guest/VM discover and use > > conditional operations related ISA extensions (namely XVentanaCondOps > > and Zicond). > > > > To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1 > > branch at: https://github.com/avpatel/kvmtool.git > > > > These patches are based upon the latest riscv_kvm_queue and can also be > > found in the riscv_kvm_condops_v3 branch at: > > https://github.com/avpatel/linux.git > > > > Changes since v2: > > - Dropped patch1, patch2, and patch5 since these patches don't meet > > the requirements of patch acceptance policy. > > > > Changes since v1: > > - Rebased the series on riscv_kvm_queue > > - Split PATCH1 and PATCH2 of v1 series into two patches > > - Added separate test configs for XVentanaCondOps and Zicond in PATCH7 > > of v1 series. > > > > Anup Patel (6): > > dt-bindings: riscv: Add Zicond extension entry > > RISC-V: Detect Zicond from ISA string > > RISC-V: KVM: Allow Zicond extension for Guest/VM > > KVM: riscv: selftests: Add senvcfg register to get-reg-list test > > KVM: riscv: selftests: Add smstateen registers to get-reg-list test > > KVM: riscv: selftests: Add condops extensions to get-reg-list test > > Queued this series for Linux-6.7 I have created shared tag kvm-riscv-shared-tag-6.7 in the KVM RISC-V repo at: https://github.com/kvm-riscv/linux.git This shared tag is based on 6.6-rc5 and contains following 4 patches: dt-bindings: riscv: Add Zicond extension entry RISC-V: Detect Zicond from ISA string dt-bindings: riscv: Add smstateen entry RISC-V: Detect Smstateen extension Thanks, Anup > > Thanks, > Anup > > > > > .../devicetree/bindings/riscv/extensions.yaml | 6 +++ > > arch/riscv/include/asm/hwcap.h | 1 + > > arch/riscv/include/uapi/asm/kvm.h | 1 + > > arch/riscv/kernel/cpufeature.c | 1 + > > arch/riscv/kvm/vcpu_onereg.c | 2 + > > .../selftests/kvm/riscv/get-reg-list.c | 54 +++++++++++++++++++ > > 6 files changed, 65 insertions(+) > > > > -- > > 2.34.1 > >
Hello: This series was applied to riscv/linux.git (fixes) by Anup Patel <anup@brainfault.org>: On Tue, 3 Oct 2023 09:22:20 +0530 you wrote: > This series extends KVM RISC-V to allow Guest/VM discover and use > conditional operations related ISA extensions (namely XVentanaCondOps > and Zicond). > > To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1 > branch at: https://github.com/avpatel/kvmtool.git > > [...] Here is the summary with links: - [v3,1/6] dt-bindings: riscv: Add Zicond extension entry https://git.kernel.org/riscv/c/00c6f39c8247 - [v3,2/6] RISC-V: Detect Zicond from ISA string https://git.kernel.org/riscv/c/662a601aa355 - [v3,3/6] RISC-V: KVM: Allow Zicond extension for Guest/VM https://git.kernel.org/riscv/c/df68f4d8cb49 - [v3,4/6] KVM: riscv: selftests: Add senvcfg register to get-reg-list test https://git.kernel.org/riscv/c/4d554e0226e6 - [v3,5/6] KVM: riscv: selftests: Add smstateen registers to get-reg-list test https://git.kernel.org/riscv/c/e1a8db0c9a0e - [v3,6/6] KVM: riscv: selftests: Add condops extensions to get-reg-list test https://git.kernel.org/riscv/c/2b3f2b78ec93 You are awesome, thank you!