| Message ID | 20240110133128.286657-1-jeeheng.sia@starfivetech.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Basic clock and reset support for StarFive JH8100 RISC-V SoC | expand |
Quoting Sia Jee Heng (2024-01-10 05:31:12) > This patch series enabled basic clock & reset support for StarFive > JH8100 SoC. > > This patch series depends on the Initial device tree support for > StarFive JH8100 SoC patch series which can be found at [1]. > > As it is recommended to refrain from merging fundamental patches like > Device Tree, Clock & Reset, and PINCTRL tested on FPGA/Emulator, into the > RISC-V Mainline, this patch series has been renamed to "RFC" patches. Yet, > thanks to the reviewers who have reviewed the patches at [2]. The changes > are captured below. I don't think that's what should be happening. Instead, clk patches should be sent to clk maintainers, reset patches to reset maintainers, pinctrl patches to pinctrl maintainers, etc. The DTS can be sent later when it's no longer an FPGA/Emulator? Right now I'm ignoring this series because it's tagged as an RFC.
On Thu, Apr 11, 2024 at 12:40:09AM -0700, Stephen Boyd wrote: > Quoting Sia Jee Heng (2024-01-10 05:31:12) > > This patch series enabled basic clock & reset support for StarFive > > JH8100 SoC. > > > > This patch series depends on the Initial device tree support for > > StarFive JH8100 SoC patch series which can be found at [1]. > > > > As it is recommended to refrain from merging fundamental patches like > > Device Tree, Clock & Reset, and PINCTRL tested on FPGA/Emulator, into the > > RISC-V Mainline, this patch series has been renamed to "RFC" patches. Yet, > > thanks to the reviewers who have reviewed the patches at [2]. The changes > > are captured below. > > I don't think that's what should be happening. Instead, clk patches > should be sent to clk maintainers, reset patches to reset maintainers, > pinctrl patches to pinctrl maintainers, etc. The DTS can be sent later > when it's no longer an FPGA/Emulator? Right now I'm ignoring this series > because it's tagged as an RFC. Since this comes back to something I said, what I didn't want to happen was a bunch of pinctrl/clock/reset dt-binding headers that getting merged (and therefore exported to other projects) and then have those change later on when the chip was taped out. I don't really care if the drivers themselves get merged. If the JH8100 is being taped out soon (or already has been internally) and there's unlikely to be any changes, there's not really a reason to block the binding headers any more.
Quoting Conor Dooley (2024-04-11 03:29:51) > On Thu, Apr 11, 2024 at 12:40:09AM -0700, Stephen Boyd wrote: > > Quoting Sia Jee Heng (2024-01-10 05:31:12) > > > This patch series enabled basic clock & reset support for StarFive > > > JH8100 SoC. > > > > > > This patch series depends on the Initial device tree support for > > > StarFive JH8100 SoC patch series which can be found at [1]. > > > > > > As it is recommended to refrain from merging fundamental patches like > > > Device Tree, Clock & Reset, and PINCTRL tested on FPGA/Emulator, into the > > > RISC-V Mainline, this patch series has been renamed to "RFC" patches. Yet, > > > thanks to the reviewers who have reviewed the patches at [2]. The changes > > > are captured below. > > > > I don't think that's what should be happening. Instead, clk patches > > should be sent to clk maintainers, reset patches to reset maintainers, > > pinctrl patches to pinctrl maintainers, etc. The DTS can be sent later > > when it's no longer an FPGA/Emulator? Right now I'm ignoring this series > > because it's tagged as an RFC. > > Since this comes back to something I said, what I didn't want to happen > was a bunch of pinctrl/clock/reset dt-binding headers that getting merged > (and therefore exported to other projects) and then have those change > later on when the chip was taped out. Ah ok. > I don't really care if the drivers > themselves get merged. If the JH8100 is being taped out soon (or already > has been internally) and there's unlikely to be any changes, there's not > really a reason to block the binding headers any more. > The binding headers are sometimes required for the drivers, so the driver can't be merged then.
This patch series enabled basic clock & reset support for StarFive JH8100 SoC. This patch series depends on the Initial device tree support for StarFive JH8100 SoC patch series which can be found at [1]. As it is recommended to refrain from merging fundamental patches like Device Tree, Clock & Reset, and PINCTRL tested on FPGA/Emulator, into the RISC-V Mainline, this patch series has been renamed to "RFC" patches. Yet, thanks to the reviewers who have reviewed the patches at [2]. The changes are captured below. StarFive JH8100 shares a similar clock and reset design with JH7110. To facilitate the reuse of the file and its functionalities, files containing the 'jh71x0' naming convention are renamed to use the 'common' wording. Internal functions that contain the 'jh71x0' naming convention are renamed to use 'starfive.' This is accomplished through patches 1, 2, 3, and 4. Patch 5 adds documentation to describe System (SYSCRG) Clock & Reset binding. Patch 6 adds SYSCRG clock driver. patch 7 adds documentation to describe North-West (NWCRG) Clock & Reset binding. Patch 8 adds NWCRG clock driver. patch 9 adds documentation to describe North-East (NECRG) Clock & Reset binding. Patch 10 adds NECRG clock driver. patch 11 adds documentation to describe South-West (SWCRG) Clock & Reset binding. Patch 12 adds SWCRG clock driver. patch 13 adds documentation to describe Always-On (AON) Clock & Reset binding. Patch 14 adds AON clock driver. Patch 15 adds support for the auxiliary reset driver. Patch 16 adds clocks and reset nodes to the JH8100 device tree. Changes since RFC V2: - Renamed the patch series to "RFC v3" because the reviewer suggested patch series at [3] to be RFC v2 instead. - Added the "Reviewed-by" tag from Krzysztof for patches 5, 7, 9, 11, and 13. - Renamed the clock nodes to clock-controller to align with the name in the dt-binding YAML documentation. Changes since [2]: - Renamed the patch series to "RFC" patches. - Added the "Reviewed-by" tag from Emil for patches 1, 2 3 & 4. - Removed clk_ prefixes. - Used 4 spaces for example indentation in dt-binding documentation. - Used the same license in dt-binding. - Moved number of clocks from binding to source file. - Moved number of resets from binding ro source file. - Removed the subfolder for new clock files. - Followed the JH71xx files naming convention. - Followed the JH71xx clock naming conventions. - Followed the JH71xx resets naming conventions. - Moved the PLL fixed clock from the source file to Device Tree. - Dropped clk.dtsi and moved the clocks node to SoC.dtsi. [1] https://lore.kernel.org/lkml/20231201121410.95298-1-jeeheng.sia@starfivetech.com/ [2] https://lore.kernel.org/lkml/20231206115000.295825-1-jeeheng.sia@starfivetech.com/ [3] https://lore.kernel.org/lkml/20231226053848.25089-1-jeeheng.sia@starfivetech.com/ Sia Jee Heng (16): reset: starfive: Rename file name "jh71x0" to "common" reset: starfive: Convert the word "jh71x0" to "starfive" clk: starfive: Rename file name "jh71x0" to "common" clk: starfive: Convert the word "jh71x0" to "starfive" dt-bindings: clock: Add StarFive JH8100 System clock and reset generator clk: starfive: Add JH8100 System clock generator driver dt-bindings: clock: Add StarFive JH8100 North-West clock and reset generator clk: starfive: Add JH8100 North-West clock generator driver dt-bindings: clock: Add StarFive JH8100 North-East clock and reset generator clk: starfive: Add JH8100 North-East clock generator driver dt-bindings: clock: Add StarFive JH8100 South-West clock and reset generator clk: starfive: Add JH8100 South-West clock generator driver dt-bindings: clock: Add StarFive JH8100 Always-On clock and reset generator clk: starfive: Add JH8100 Always-On clock generator driver reset: starfive: Add StarFive JH8100 reset driver riscv: dts: starfive: jh8100: Add clocks and resets nodes .../clock/starfive,jh8100-aoncrg.yaml | 74 +++ .../bindings/clock/starfive,jh8100-necrg.yaml | 153 +++++ .../bindings/clock/starfive,jh8100-nwcrg.yaml | 119 ++++ .../bindings/clock/starfive,jh8100-swcrg.yaml | 64 +++ .../clock/starfive,jh8100-syscrg.yaml | 77 +++ MAINTAINERS | 15 + arch/riscv/boot/dts/starfive/jh8100.dtsi | 313 +++++++++++ drivers/clk/starfive/Kconfig | 45 +- drivers/clk/starfive/Makefile | 8 +- drivers/clk/starfive/clk-starfive-common.c | 327 +++++++++++ drivers/clk/starfive/clk-starfive-common.h | 130 +++++ .../clk/starfive/clk-starfive-jh7100-audio.c | 127 ++--- drivers/clk/starfive/clk-starfive-jh7100.c | 503 ++++++++--------- .../clk/starfive/clk-starfive-jh7110-aon.c | 62 +-- .../clk/starfive/clk-starfive-jh7110-isp.c | 72 +-- .../clk/starfive/clk-starfive-jh7110-stg.c | 94 ++-- .../clk/starfive/clk-starfive-jh7110-sys.c | 523 +++++++++--------- .../clk/starfive/clk-starfive-jh7110-vout.c | 74 +-- drivers/clk/starfive/clk-starfive-jh7110.h | 4 +- drivers/clk/starfive/clk-starfive-jh71x0.c | 327 ----------- drivers/clk/starfive/clk-starfive-jh71x0.h | 123 ---- .../clk/starfive/clk-starfive-jh8100-aon.c | 256 +++++++++ drivers/clk/starfive/clk-starfive-jh8100-ne.c | 499 +++++++++++++++++ drivers/clk/starfive/clk-starfive-jh8100-nw.c | 237 ++++++++ drivers/clk/starfive/clk-starfive-jh8100-sw.c | 134 +++++ .../clk/starfive/clk-starfive-jh8100-sys.c | 415 ++++++++++++++ drivers/clk/starfive/clk-starfive-jh8100.h | 11 + drivers/reset/starfive/Kconfig | 14 +- drivers/reset/starfive/Makefile | 4 +- ...rfive-jh71x0.c => reset-starfive-common.c} | 68 +-- .../reset/starfive/reset-starfive-common.h | 14 + .../reset/starfive/reset-starfive-jh7100.c | 4 +- .../reset/starfive/reset-starfive-jh7110.c | 8 +- .../reset/starfive/reset-starfive-jh71x0.h | 14 - .../reset/starfive/reset-starfive-jh8100.c | 108 ++++ .../dt-bindings/clock/starfive,jh8100-crg.h | 421 ++++++++++++++ .../dt-bindings/reset/starfive,jh8100-crg.h | 118 ++++ ...rfive-jh71x0.h => reset-starfive-common.h} | 10 +- 38 files changed, 4327 insertions(+), 1242 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-aoncrg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-necrg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-nwcrg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-swcrg.yaml create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh8100-syscrg.yaml create mode 100644 drivers/clk/starfive/clk-starfive-common.c create mode 100644 drivers/clk/starfive/clk-starfive-common.h delete mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.c delete mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.h create mode 100644 drivers/clk/starfive/clk-starfive-jh8100-aon.c create mode 100644 drivers/clk/starfive/clk-starfive-jh8100-ne.c create mode 100644 drivers/clk/starfive/clk-starfive-jh8100-nw.c create mode 100644 drivers/clk/starfive/clk-starfive-jh8100-sw.c create mode 100644 drivers/clk/starfive/clk-starfive-jh8100-sys.c create mode 100644 drivers/clk/starfive/clk-starfive-jh8100.h rename drivers/reset/starfive/{reset-starfive-jh71x0.c => reset-starfive-common.c} (55%) create mode 100644 drivers/reset/starfive/reset-starfive-common.h delete mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.h create mode 100644 drivers/reset/starfive/reset-starfive-jh8100.c create mode 100644 include/dt-bindings/clock/starfive,jh8100-crg.h create mode 100644 include/dt-bindings/reset/starfive,jh8100-crg.h rename include/soc/starfive/{reset-starfive-jh71x0.h => reset-starfive-common.h} (50%)