[RFC,0/6] riscv: perf: Add support for Control Transfer Records Ext.

Message

Rajnesh Kanwal May 29, 2024, 6:53 p.m. UTC

This series enables Control Transfer Records extension support on riscv
platform. CTR extension is similar to Arch LBR in x86 and BRBE in ARM. The
Extension is in stable state but not yet frozen and the latest release can
be found here [0]

CTR extension provides a method to record a limited branch history in
register-accessible internal core storage. CTR allows to selectively record
branches using filter bitmask. On a counter overflow, CTR stops recording and
the kernel samples the recorded branches in the overflow handler. CTR also
supports RASEMU mode. In RASEMU mode, a call is recorded on every function call
and on every return an entry is removed from the buffer.

CTR extension depends on couple of other extensions:

1. S[m|s]csrind : The indirect CSR extension [1] which defines additional
   ([M|S|VS]IREG2-[M|S|VS]IREG6) register to address size limitation of
   RISC-V CSR address space. CTR access ctrsource, ctrtartget and ctrdata
   CSRs using sscsrind extension.

2. Smstateen: The mstateen bit[54] controls the access to the CTR ext to
   S-mode.

3. Sscofpmf: Counter overflow and privilege mode filtering. [2]

The series is based on Smcdeleg/Ssccfg counter delegation extension [3]
patches [4]. CTR itself doesn't depend on counter delegation support. This
rebase is basically to include the Smcsrind patches.

The last patch is in the perf tool to allow processing 256 entries. Without
this perf seems to consider that sample as corrupted and discards it.

Here is the link to a quick guide [5] to setup and run a basic perf demo on
Linux to use CTR Ext.

The Qemu patches can be found here:
https://github.com/rajnesh-kanwal/qemu/tree/ctr_upstream

The opensbi patch can be found here:
https://github.com/rajnesh-kanwal/opensbi/tree/ctr_upstream

The Linux kernel patches can be found here:
https://github.com/rajnesh-kanwal/linux/tree/ctr_upstream

[0]: https://github.com/riscv/riscv-control-transfer-records/release
[1]: https://github.com/riscv/riscv-indirect-csr-access
[2]: https://github.com/riscvarchive/riscv-count-overflow/tree/main
[3]: https://github.com/riscv/riscv-smcdeleg-ssccfg
[4]: https://lore.kernel.org/lkml/[e-mail]/
[5]: https://github.com/rajnesh-kanwal/linux/wiki/Running-CTR-basic-demo-on-QEMU-RISC%E2%80%90V-Virt-machine

Rajnesh Kanwal (6):
  perf: Increase the maximum number of samples to 256.
  riscv: perf: Add Control transfer records CSR definations.
  riscv: perf: Add Control Transfer Records extension parsing
  riscv: perf: Add infrastructure for Control Transfer Record
  riscv: perf: Add driver for Control Transfer Records Ext.
  riscv: perf: Integrate CTR Ext support in riscv_pmu_dev driver

 MAINTAINERS                     |   1 +
 arch/riscv/include/asm/csr.h    |  83 ++++++
 arch/riscv/include/asm/hwcap.h  |   4 +
 arch/riscv/kernel/cpufeature.c  |   2 +
 drivers/perf/Kconfig            |  11 +
 drivers/perf/Makefile           |   1 +
 drivers/perf/riscv_ctr.c        | 469 ++++++++++++++++++++++++++++++++
 drivers/perf/riscv_pmu_common.c |  18 +-
 drivers/perf/riscv_pmu_dev.c    |  84 +++++-
 include/linux/perf/riscv_pmu.h  |  49 ++++
 tools/perf/util/machine.c       |  21 +-
 11 files changed, 722 insertions(+), 21 deletions(-)
 create mode 100644 drivers/perf/riscv_ctr.c