[v2,0/2] tools: Add barrier implementations for riscv

Message ID	20240806-optimize_ring_buffer_read_riscv-v2-0-ca7e193ae198@rivosinc.com (mailing list archive)
Headers	show Return-Path: <linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org> From: Charlie Jenkins <charlie@rivosinc.com> Subject: [PATCH v2 0/2] tools: Add barrier implementations for riscv Date: Tue, 06 Aug 2024 15:01:22 -0700 Message-Id: <20240806-optimize_ring_buffer_read_riscv-v2-0-ca7e193ae198@rivosinc.com> MIME-Version: 1.0 To: Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Andrea Parri <parri.andrea@gmail.com> Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Charlie Jenkins <charlie@rivosinc.com> Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org> Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org
Series	tools: Add barrier implementations for riscv \| expand [v2,0/2] tools: Add barrier implementations for riscv [v2,1/2] tools: Add riscv barrier implementation [v2,2/2] tools: Optimize ring buffer for riscv

Message ID

20240806-optimize_ring_buffer_read_riscv-v2-0-ca7e193ae198@rivosinc.com (mailing list archive)

Headers

From: Charlie Jenkins <charlie@rivosinc.com>
Subject: [PATCH v2 0/2] tools: Add barrier implementations for riscv
Date: Tue, 06 Aug 2024 15:01:22 -0700
Message-Id: 
 <20240806-optimize_ring_buffer_read_riscv-v2-0-ca7e193ae198@rivosinc.com>
MIME-Version: 1.0
To: Paul Walmsley <paul.walmsley@sifive.com>,
 Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>,
 Andrea Parri <parri.andrea@gmail.com>
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
 Charlie Jenkins <charlie@rivosinc.com>
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Sender: "linux-riscv" <linux-riscv-bounces@lists.infradead.org>
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 linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org

Series

tools: Add barrier implementations for riscv | expand

Message

Charlie Jenkins Aug. 6, 2024, 10:01 p.m. UTC

Add support for riscv specific barrier implementations to the tools
tree, so that fence instructions can be emitted for synchronization.

Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
---
Changes in v2:
- Fix typo in commit message
- Link to v1: https://lore.kernel.org/r/20240729-optimize_ring_buffer_read_riscv-v1-0-6bbc0f2434ee@rivosinc.com

---
Charlie Jenkins (2):
      tools: Add riscv barrier implementation
      tools: Optimize ring buffer for riscv

 tools/arch/riscv/include/asm/barrier.h | 39 ++++++++++++++++++++++++++++++++++
 tools/arch/riscv/include/asm/fence.h   | 13 ++++++++++++
 tools/include/asm/barrier.h            |  2 ++
 tools/include/linux/ring_buffer.h      |  2 +-
 4 files changed, 55 insertions(+), 1 deletion(-)
---
base-commit: 0c3836482481200ead7b416ca80c68a29cfdaabd
change-id: 20240725-optimize_ring_buffer_read_riscv-228491c4eb6e